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| this is information on a product in full production. april 2014 docid025832 rev 2 1/117 stm32f042x arm ? -based 32-bit mcu, up to 32 kb flash, crystal-less usb fs 2.0, can, 8 timers, adc & comm. interfaces, 2.0 - 3.6 v datasheet - production data features ? core: arm ? 32-bit cortex ? -m0 cpu, frequency up to 48 mhz ? memories ? 16 to 32 kbytes of flash memory ? 6 kbytes of sram with hw parity ? crc calculation unit ? reset and power management ? digital and i/os supply: v dd = 2 v to 3.6 v ? analog supply: v dda = v dd to 3.6 v ? selected i/os: v ddio2 = 1.65 v to 3.6 v ? power-on/power down reset (por/pdr) ? programmable voltage detector (pvd) ? low power modes: sleep, stop, standby ?v bat supply for rtc and backup registers ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x6 pll option ? internal 40 khz rc oscillator ? internal 48 mhz oscillator with automatic trimming based on ext. synchronization ? up to 37 fast i/os ? all mappable on external interrupt vectors ? up to 37 i/os with 5 v tolerant capability and 8 with independent supply v ddio2 ? 5-channel dma controller ? one 12-bit, 1.0 s adc (up to 10 channels) ? conversion range: 0 to 3.6 v ? separate analog supply: 2.4 v to 3.6 v ? up to 14 capacitive sensing channels for touchkey, linear and rotary touch sensors ? calendar rtc with alarm and periodic wakeup from stop/standby ? nine timers ? one 16-bit advanced-control timer for six channel pwm output ? one 32-bit and four 16-bit timers, with up to four ic/oc, ocn, usable for ir control decoding ? independent and system watchdog timers ? systick timer ? communication interfaces ? one i 2 c interface supporting fast mode plus (1 mbit/s) with 20 ma current sink, smbus/pmbus and wakeup ? two usarts supporting master synchronous spi and modem control; one with iso7816 interface, lin, irda, auto baud rate detection and wakeup feature ? two spis (18 mbit/s) with four to 16 programmable bit frames, one with i 2 s interface multiplexed ? can interface ? usb 2.0 full-speed interface, able to run from internal 48 mhz oscillator and with bcd and lpm support ? hdmi cec, wakeup on header reception ? serial wire debug (swd) ? 96-bit unique id ? all packages ecopack ? 2 table 1. device summary reference part number stm32f042xx stm32f042f4, stm32f042g4, stm32f042k4, stm32f042t4, stm32f042c4 stm32f042f6, stm32f042g6, stm32f042k6, stm32f042t6, stm32f042c6 lqfp48 7x7 ufqfpn48 7x7 wlcsp36 ufqfpn32 5x5 ufqfpn28 4x4 tssop20 lqfp32 5x5 www.st.com
contents stm32f042xx 2/117 docid025832 rev 2 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 arm? cortex?-m0 core with embedded flash and sram . . . . . . . . . . . 13 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 14 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.2 power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 18 3.9.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 18 3.10 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10.3 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12.1 advanced-control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.12.2 general-purpose timers (tim2..3, tim14, 16, 17) . . . . . . . . . . . . . . . . . 22 3.12.3 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.12.4 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.12.5 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23 3.14 inter-integrated circuit interfaces (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 docid025832 rev 2 3/117 stm32f042xx contents 4 3.15 universal synchronous/asynchronous receiver transmitters (usart) . . 25 3.16 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) . 26 3.17 high-definition multimedia interface (hdmi) - consumer electronics control (cec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20 clock recovery system (crs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.21 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 50 6.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 50 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.8 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 contents stm32f042xx 4/117 docid025832 rev 2 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.16 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.17 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.18 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.19 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.20 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 docid025832 rev 2 5/117 stm32f042xx list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f042x device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. capacitive sensing gpios available on stm32f042x devices . . . . . . . . . . . . . . . . . . . . . 20 table 6. no. of capacitive sensing channels available on stm32f042x devices. . . . . . . . . . . . . . . 21 table 7. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. stm32f042x i 2 c implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. stm32f042x usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. stm32f042x spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 13. stm32f042x pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. alternate functions selected through gpioa_afr registers for port a . . . . . . . . . . . . . . . 38 table 15. alternate functions selected through gpiob_afr registers for port b . . . . . . . . . . . . . . . 39 table 16. alternate functions selected through gpiof_afr registers for port f. . . . . . . . . . . . . . . . 40 table 17. stm32f042x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 19. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 20. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 23. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 24. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 25. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 26. typical and maximum current consumption from v dd supply at v dd = 3.6 v . . . . . . . . . . 52 table 27. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . 54 table 28. typical and maximum consumption in stop and standby modes . . . . . . . . . . . . . . . . . . . 55 table 29. typical and maximum current consumption from the v bat supply . . . . . . . . . . . . . . . . . . 56 table 30. typical current consumption, code executing from flash, running from hse 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 31. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 32. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 33. low-power mode wakeup timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 34. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 35. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 36. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 37. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 38. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 39. hsi14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 40. hsi48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 41. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 42. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 43. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 44. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 45. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 46. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 47. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 list of tables stm32f042xx 6/117 docid025832 rev 2 table 48. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 49. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 50. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 51. output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 52. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 53. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 54. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 55. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 56. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 57. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 58. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 59. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 60. iwdg min/max timeout period at 40 khz (lsi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 61. wwdg min/max timeout value at 48 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 62. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 63. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 64. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 65. lqfp48 ? 7 mm x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . . . . 95 table 66. ufqfpn48 ? 7 mm x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . 99 table 67. wlcsp36, 0.4 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 68. lqfp32 ? 7 mm x 7 mm 32-pin low-profile quad flat package mechanical data . . . . . . . 104 table 69. ufqfpn32 ? 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 70. ufqfpn28 ? 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 71. tssop20 ? 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . 112 table 72. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 73. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 74. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 docid025832 rev 2 7/117 stm32f042xx list of figures 8 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. lqfp48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4. ufqfpn48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5. wlcsp36 36-pin package ball-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6. lqfp32 32-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7. ufqfpn32 32-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 8. uqfpn28 28-pin package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 9. tssop20 20-pin package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 10. stm32f042x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 11. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 13. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 14. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 15. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 16. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 17. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 figure 18. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 19. hsi oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 20. hsi14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 21. hsi48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 22. tc and tta i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 23. five volt tolerant (ft and ftf) i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 24. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 25. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 26. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 27. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 28. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 29. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 30. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 31. i2s slave timing diagram (philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 figure 32. i2s master timing diagram (philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 33. lqfp48 ? 7 mm x 7 mm, 48 pin low-profile quad flat package outline. . . . . . . . . . . . . . . . 95 figure 34. lqfp48 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 35. lqfp48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 36. ufqfpn48 ? 7 mm x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . 98 figure 37. ufqfpn48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 38. ufqfpn48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 0 figure 39. wlcsp36 - 0.4 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 40. wlcsp36 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 03 figure 41. lqfp32 ? 7 mm x 7 mm 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 104 figure 42. lqfp32 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 figure 43. lqfp32 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 44. ufqfpn32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline . . 107 figure 45. ufqfpn32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 46. ufqfpn32 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 figure 47. ufqfpn28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline . . 109 figure 48. ufqfpn28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 list of figures stm32f042xx 8/117 docid025832 rev 2 figure 49. ufqfpn28 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 figure 50. tssop20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 51. tssop20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 52. tssop20 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 docid025832 rev 2 9/117 stm32f042xx introduction 27 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f042x microcontrollers. this document should be read in conjunction with the stm32f0xxxx reference manual (rm0091). the reference manual is available from the stmicroelectronics website at www.st.com . for information on the arm ? cortex ? -m0 core, please refer to the cortex ? -m0 technical reference manual, available from arm website at www.arm.com . description stm32f042xx 10/117 docid025832 rev 2 2 description the stm32f042x microcontrollers incorporate the high-performance arm ? cortex ? -m0 32-bit risc core operating at a 48 mhz frequency, high-speed embedded memories (up to 32 kbytes of flash memory and 6 kbytes of sram), and an extensive range of enhanced peripherals and i/os. all devices offer standard communication interfaces (one i 2 c, two spis/one i2s, one hdmi cec and two usarts), one usb full speed device (crystal-less), one can, one 12-bit adc, four general-purpose 16-bit timers, a 32-bit timer and an advanced-control pwm timer. the stm32f042x microcontrollers operate in the -40 to +85 c and -40 to +105 c temperature ranges from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving modes allows the design of low-power applications. the stm32f042x microcontrollers include devices in seven different packages ranging from 20 pins to 48 pins with a die form also available upon request. depending on the device chosen, different sets of peripherals are included. the description below provides an overview of the complete range of stm32f042x peripherals proposed. these features make the stm32f042x microcontrollers suitable for a wide range of applications such as application control and user interfaces, handheld equipment, a/v receivers and digital tv, pc peripherals, gaming and gps platforms, industrial applications, plcs, inverters, printers, scanners, alarm systems, video intercoms, and hvacs. docid025832 rev 2 11/117 stm32f042xx description 27 table 2. stm32f042x device features and peripheral counts peripheral stm32f042fx stm32f042g stm32f042k stm32f042t stm32f042c flash (kbytes) 16 32 16 32 16 32 16 32 16 32 sram (kbytes) 66666 timers advanced control 1 (16-bit) general purpose 4 (16-bit) 1 (32-bit) comm. interfaces spi [i2s] (1) 1 [1] 2 [1] i 2 c1 usart 2 can 1 usb 1 cec 1 12-bit adc (number of channels) 1 (9 ext. + 3 int.) 1 (10 ext. + 3 int.) gpios 16 24 26 28 30 38 capacitive sensing channels 711 13 14 14 14 max. cpu frequency 48 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: -40 c to 85 c / -40 c to 105 c junction temperature: -40 c to 105 c / -40 c to 125 c packages tssop20 uqfpn28 lqfp32 uqfpn32 wlcsp36 lqfp48 ufqfpn48 1. the spi1 interface can be used either in spi mode or in i2s audio mode. description stm32f042xx 12/117 docid025832 rev 2 figure 1. block diagram 0 6 y 9 f k d q q h o v f r p s o f k d q q h o v % 5 . ( 7 5 l q s x w d v $ ) f k ( 7 5 d v $ ) f k ( 7 5 d v $ ) f k d q q h o d v $ ) f k d q q h o f r p s o % 5 . d v $ ) f k d q q h o f r p s o % 5 . d v $ ) , 5 b 2 8 7 d v $ ) 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 6 & / 6 ' $ 6 0 % $ p $ i r u ) 0 d v $ ) & ( & d v $ ) # 9 ' ' , 2 # 9 ' ' $ $ + % 3 & / . $ 3 % 3 & / . $ ' & & / . 8 6 $ 5 7 & / . + & / . ) & / . & ( & & / . 3 $ > @ 3 % > @ 3 & > @ 3 ) > @ j u r x s v r i f k d q q h o v 6 < 1 & $ ) 0 2 6 , 6 ' 0 , 6 2 0 & . 6 & . & . 1 6 6 : 6 d v $ ) # 9 ' ' $ 9 ' ' $ 9 6 6 $ * 3 ' 0 $ f k d q q h o v & 2 5 7 ( ; 0 & 3 8 i 0 $ ; 0 + ] 6 h u l d o : l u h ' h e x j 1 9 , & * 3 , 2 s r u w $ * 3 , 2 s r u w % * 3 , 2 s r u w & * 3 , 2 s r u w ) 7 r x f k 6 h q v l q j & r q w u r o o h u 3 $ ' $ q d o r j v z l w f k h v ( ; 7 , 7 : . 8 3 6 3 , , 6 6 3 , 6 < 6 & ) * , ) ' % * 0 & 8 : , q g r z : ' * $ 3 % $ + % & 5 & 5 ( 6 ( 7 & / 2 & . & 2 1 7 5 2 / 3 : 0 7 , 0 ( 5 7 , 0 ( 5 e l w 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 8 6 $ 5 7 8 6 $ 5 7 , & + ' 0 , & ( & 3 r z h u & r q w u r o o h u ; 7 $ / 2 6 & 0 + ] , q g : l q g r z : ' * 6 8 3 3 / < 6 8 3 ( 5 9 , 6 , 2 1 3 9 ' 3 2 5 3 ' 5 3 2 : ( 5 9 2 / 7 5 ( * 9 7 2 9 5 & + 6 0 + ] 5 & + 6 0 + ] 5 & / 6 3 / / ) o d v k l q w h u i d f h ) o d v k * 3 / 8 s w r . % e l w v 2 e o 6 5 $ 0 . % 6 5 $ 0 f r q w u r o o h u 7 h p s v h q v r u , ) e l w $ ' & 6 : & / . 6 : ' , 2 d v $ ) $ ' l q s x w v $ + % g h f r g h u % x v p d w u l [ # 9 ' ' $ # 9 ' ' , 2 9 ' ' 3 2 5 5 h v h w , q w 9 ' ' , 2 w r 9 9 6 6 1 5 6 7 9 ' ' $ 9 6 6 $ 2 6 & b , 1 3 ) 2 6 & b 2 8 7 3 ) 9 % $ 7 w r 9 2 6 & b , 1 2 6 & b 2 8 7 7 $ 0 3 ( 5 5 7 & $ / $ 5 0 2 8 7 5 7 & % d f n x s u h j 5 7 & l q w h u i d f h ; 7 $ / n + ] # 9 6 : % [ & $ 1 7 ; 5 ; d v $ ) 8 6 % 3 + < ' ' 8 6 % # 9 ' ' 8 6 % 8 6 % & / . 5 & + 6 0 + ] 9 ' ' 8 6 % 2 . , 1 & 5 6 6 < 1 & 6 5 $ 0 % 6 5 $ 0 % 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) docid025832 rev 2 13/117 stm32f042xx functional overview 27 3 functional overview 3.1 arm ? cortex ? -m0 core with embedded flash and sram the arm ? cortex ? -m0 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm ? cortex ? -m0 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f0xx family has an embedded arm core and is therefore compatible with all arm tools and software. figure 1 shows the general block diagram of the device family. 3.2 memories the device has the following features: ? 6 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications. ? the non-volatile memory is divided into two arrays: ? 16 to 32 kbytes of embedded flash memory for programs and data ? option bytes the option bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, the flash memory cannot be read from or written to if either debug features are connected or boot in ram is selected ? level 2: chip readout protection, debug features (cortex-m0 serial wire) and boot in ram selection disabled 3.3 boot modes at startup, the boot pin and boot selector option bits are used to select one of the three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot pin is shared with the standard gpio and can be disabled through the boot selector option bits. the boot loader is located in system memory. it is used to reprogram the flash memory by using usart on pins pa14/pa15 or pa9/pa10, i2c on pins pb6/pb7 or through the usb dfu interface. functional overview stm32f042xx 14/117 docid025832 rev 2 3.4 cyclic redundancy check calculation unit (crc) the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a crc-32 (ethernet) polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.5 power management 3.5.1 power supply schemes ? v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. ? v dda = 2.0 to 3.6 v: external analog power supply for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc is used). the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. ? v ddio2 = 1.65 to 3.6 v: external power supply for marked i/os. provided externally through the vddio2 pin. the v ddio2 voltage level is completely independent from v dd or v dda , but it must not be provided without a valid supply on v dd . refer to the pinout diagrams or tables for concerned i/os list. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 3.5.2 power supply supervisors the device has integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the application design ensures that v dda is higher than or equal to v dd . the v ddio2 supply is monitored and compared with the internal reference voltage (v refint ). when the v ddio2 is below this threshold, all the i/os supplied from this rail are disabled by hardware. the output of this comparator is connected to exti line 31 and it can be used to generate an interrupt. the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. docid025832 rev 2 15/117 stm32f042xx functional overview 27 3.5.3 voltage regulator the regulator has two operating modes and it is always enabled after reset. ? main (mr) is used in normal operating mode (run). ? low power (lpr) can be used in stop mode where the power demand is reduced. in standby mode, it is put in power down mode. in this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and sram are lost). 3.5.4 low-power modes the stm32f042x microcontrollers support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves very low power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti lines. the exti line source can be one of the 16 external lines, the pvd output, rtc alarm, i2c1, usart1 or the cec. the i2c1, usart1 and the cec can be configured to enable the hsi rc oscillator for processing incoming data. if this is used when the voltage regulator is put in low power mode, the regulator is first switched to normal mode before the clock is provided to the given peripheral. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the rtc domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pins, or an rtc event occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. functional overview stm32f042xx 16/117 docid025832 rev 2 3.6 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillator. a software interrupt is generated if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). several prescalers allow the application to configure the frequency of the ahb and the apb domains. the maximum frequency of the ahb and the apb domains is 48 mhz. additionally, also the internal rc 48 mhz oscillator can be selected for system clock or pll input source. this oscillator can be automatically fine-trimmed by the means of the crs peripheral using the external synchronization. docid025832 rev 2 17/117 stm32f042xx functional overview 27 figure 2. clock tree 3.7 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. 0 + ] + 6 ( 2 6 & 2 6 & b , 1 2 6 & b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 0 + ] + 6 , 5 & w r , : ' * 3 / / [ [ [ 3 / / 0 8 / 0 & 2 0 d l q f o r f n r x w s x w $ + % 3 / / & / . + 6 , + 6 ( + & / . 3 / / & / . w r $ + % e x v f r u h p h p r u \ d q g ' 0 $ w r $ ' & f o r f n l q s x w / 6 ( / 6 , + 6 , + 6 , + 6 ( w r 5 7 & 3 / / 6 5 & 6 : 0 & 2 6 < 6 & / . 5 7 & & / . 5 7 & 6 ( / > @ 6 < 6 & / . w r 7 , 0 , i $ 3 % s u h v f d o h u [ h o v h [ ) / , 7 ) & / . w r ) o d v k + 6 , 0 + ] + 6 , 5 & + 6 , / 6 ( w r , & w r 8 6 $ 5 7 / 6 ( + 6 , 6 < 6 & / . 3 & / . 6 < 6 & / . + 6 , 3 & / . 0 6 9 w r , 6 w r & ( & w r f r u w h [ 6 \ v w h p w l p h u ) & / . & r u w h [ i u h h u x q q l q j f o r f n w r $ 3 % s h u l s k h u d o v & 6 6 / 6 ( 2 6 & n + ] / 6 , 5 & n + ] / 6 , / 6 ( & 5 6 0 + ] + 6 , 5 & + 6 , 3 5 ( ' , 9 + 6 , 3 / / 1 2 ' , 9 s u r j u d p p l q j l q w h u i d f h w r 8 6 % 3 / / & / . + 6 , 0 & 2 3 5 ( w r 7 , 0 d v \ q f k u r q r x v $ + % s u h v f d o h u $ 3 % s u h v f d o h u functional overview stm32f042xx 18/117 docid025832 rev 2 the i/o configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 3.8 direct memory access controller (dma) the 5-channel general-purpose dmas manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. dma can be used with the main peripherals: spi, i2s, i2c, usart, all timx timers (except tim14) and adc. 3.9 interrupts and events 3.9.1 nested vectored interrupt controller (nvic) the stm32f0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m0) and 4 priority levels. ? closely coupled nvic gives low latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 extended interrupt/event controller (exti) the extended interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests and wake-up the system. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 38 gpios can be connected to the 16 external interrupt lines. 3.10 analog to digital converter (adc) the 12-bit analog to digital converter has up to 10 external and 3 internal (temperature docid025832 rev 2 19/117 stm32f042xx functional overview 27 sensor, voltage reference, vbat voltage measurement) channels and performs conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. 3.10.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connected to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the temperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.10.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc. v refint is internally connected to the adc_in17 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. table 3. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at a temperature of 30 c ( ?? 5 c), v dda = 3.3 v ( ?? 10 mv) 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at a temperature of 110 c ( ?? 5 c), v dda = 3.3 v ( ?? 10 mv) 0x1fff f7c2 - 0x1fff f7c3 table 4. internal voltage reference calibration values calibration value name description memory address vrefint_cal raw data acquired at a temperature of 30 c ( ?? 5 c), v dda = 3.3 v ( ?? 10 mv) 0x1fff f7ba - 0x1fff f7bb functional overview stm32f042xx 20/117 docid025832 rev 2 3.10.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc_in18. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. 3.11 touch sensing controller (tsc) the stm32f042x devices provide a simple solution for adding capacitive sensing functionality to any application. these devices offer up to 14 capacitive sensing channels distributed over 5 analog i/o groups. capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). the capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. to limit the cpu bandwidth usage, this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. the touch sensing controller is fully supported by the stmtouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application. table 5. capacitive sensing gpios available on stm32f042x devices group capacitive sensing signal name pin name group capacitive sensing signal name pin name 1 tsc_g1_io1 pa0 4 tsc_g4_io1 pa9 tsc_g1_io2 pa1 tsc_g4_io2 pa10 tsc_g1_io3 pa2 tsc_g4_io3 pa11 tsc_g1_io4 pa3 tsc_g4_io4 pa12 2 tsc_g2_io1 pa4 5 tsc_g5_io1 pb3 tsc_g2_io2 pa5 tsc_g5_io2 pb4 tsc_g2_io3 pa6 tsc_g5_io3 pb6 tsc_g2_io4 pa7 tsc_g5_io4 pb7 3 tsc_g3_io2 pb0 tsc_g3_io3 pb1 tsc_g3_io4 pb2 docid025832 rev 2 21/117 stm32f042xx functional overview 27 3.12 timers and watchdogs the stm32f042x devices include up to five general-purpose timers and an advanced control timer. table 7 compares the features of the advanced-control and general-purpose timers. table 6. no. of capacitive sensing channels available on stm32f042x devices analog i/o group number of capacitive sensing channels stm32f042cx lqpf48 uqfpn48 stm32f042tx wlcsp36 stm32f042kx lqfp32 uqfpn32 stm32f042gx uqfpn28 stm32f042fx tssop20 g1 33333 g2 33333 g3 2 2 1 2 10 g4 33311 g5 33330 number of capacitive sensing channels 14 14 13 14 11 7 table 7. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs advanced control tim1 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes general purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim3 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim14 16-bit up any integer between 1 and 65536 no 1 no tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 yes functional overview stm32f042xx 22/117 docid025832 rev 2 3.12.1 advanced-control timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on six channels. it has complementary pwm outputs with programmable inserted dead times. it can also be seen as a complete general-purpose timer. the four independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or center-aligned modes) ? one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pwm generator, it has full modulation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard timers which have the same architecture. the advanced control timer can therefore work together with the other timers via the timer link feature for synchronization or event chaining. 3.12.2 general-purpose timers (tim2..3, tim14, 16, 17) there are five synchronizable general-purpose timers embedded in the stm32f042x devices (see table 7 for differences). each general-purpose timer can be used to generate pwm outputs, or as simple time base. tim2, tim3 stm32f042x devices feature two synchronizable 4-channel general-purpose timers. tim2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. tim3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. they feature 4 independent channels each for input capture/output compare, pwm or one-pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim2 and tim3 general-purpose timers can work together or with the tim1 advanced- control timer via the timer link feature for synchronization or event chaining. tim2 and tim3 both have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. their counters can be frozen in debug mode. tim14 this timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim14 features one single channel for input capture/output compare, pwm or one-pulse mode output. its counter can be frozen in debug mode. tim16 and tim17 both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. docid025832 rev 2 23/117 stm32f042xx functional overview 27 they each have a single channel for input capture/output compare, pwm or one-pulse mode output. the tim16 and tim17 timers can work together via the timer link feature for synchronization or event chaining. tim16 and tim17 have a complementary output with dead-time generation and independent dma request generation. their counters can be frozen in debug mode. 3.12.3 independent watchdog (iwdg) the independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.12.4 system window watchdog (wwdg) the system window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the apb clock (pclk). it has an early warning interrupt capability and the counter can be frozen in debug mode. 3.12.5 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source (hclk or hclk/8) 3.13 real-time clock (rtc) and backup registers the rtc and the 5 backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are five 32-bit registers used to store 20 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby mode. functional overview stm32f042xx 24/117 docid025832 rev 2 the rtc is an independent bcd timer/counter. its main features are the following: ? calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatically correction for 28, 29 (leap year), 30, and 31 day of the month. ? programmable alarm with wake up from stop and standby mode capability. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. ? 2 anti-tamper detection pins with programmable filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? reference clock detection: a more precise second source clock (50 or 60 hz) can be used to enhance the calendar precision. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32 3.14 inter-integrated circuit interfaces (i 2 c) the i 2 c interface (i2c1) can operate in multimaster or slave modes. it can support standard mode (up to 100 kbit/s), fast mode (up to 400 kbit/s) and fast mode plus (up to 1 mbit/s) with 20 ma output drive on some i/os. it supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). it also includes programmable analog and digital noise filters. in addition, i2c1 provides hardware support for smbus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) generation/verification, timeouts verifications and alert protocol management. i2c1 also has a clock domain independent table 8. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes ? 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. docid025832 rev 2 25/117 stm32f042xx functional overview 27 from the cpu clock, allowing the i2c1 to wake up the mcu from stop mode on address match. the i2c interface can be served by the dma controller. 3.15 universal synchronous/asynchronous receiver transmitters (usart) the device embeds up to two universal synchronous/asynchronous receiver transmitters (usart1 and usart2), which communicate at speeds of up to 6 mbit/s. they provide hardware management of the cts, rts and rs485 de signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. usart1 supports also smartcard communication (iso 7816), irda sir endec, lin master/slave capability and auto baud rate feature, and has a clock domain independent from the cpu clock, allowing usart1 to wake up the mcu from stop mode. the usart interfaces can be served by the dma controller. refer to table 10 for the differences between usart1 and usart2. table 9. stm32f042x i 2 c implementation i2c features (1) 1. x = supported. i2c1 7-bit addressing mode x 10-bit addressing mode x standard mode (up to 100 kbit/s) x fast mode (up to 400 kbit/s) x fast mode plus with 20ma output drive i/os (up to 1 mbit/s) x independent clock x smbus x wakeup from stop x table 10. stm32f042x usart implementation usart modes/features (1) usart1 usart2 hardware flow control for modem x x continuous communication using dma x x multiprocessor communication x x synchronous mode x x smartcard mode x (2) single-wire half-duplex communication x x irda sir endec block x functional overview stm32f042xx 26/117 docid025832 rev 2 3.16 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) up to two spis are able to communicate up to 18 mbits/s in slave and master modes in full- duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. one standard i 2 s interface (multiplexed with spi1) supporting four different audio standards can operate as master or slave at half-duplex communication mode. it can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. audio sampling frequency from 8 khz up to 192 khz can be set by an 8-bit programmable linear prescaler. when operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency. refer to table 11 for the differences between spi1 and spi2. lin mode x dual clock domain and wakeup from stop mode x receiver timeout interrupt x modbus communication x auto baud rate detection x driver enable x x 1. x = supported. 2. usart1_ck is not available on 20/28 pin packages. another source of clock (for example timer output programmed to the desired clock frequency) is needed to clock the card. table 10. stm32f042x usart implementation (continued) usart modes/features (1) usart1 usart2 table 11. stm32f042x spi/i2s implementation spi features (1) 1. x = supported. spi1 spi2 hardware crc calculation x x rx/tx fifo x x nss pulse mode x x i2s mode x ti mode x x docid025832 rev 2 27/117 stm32f042xx functional overview 27 3.17 high-definition multimedia interface (hdmi) - consumer electronics control (cec) the device embeds a hdmi-cec controller that provides hardware support for the consumer electronics control (cec) protocol (supplement 1 to the hdmi standard). this protocol provides high-level control functions between all audiovisual products in an environment. it is specified to operate at low speeds with minimum processing and memory overhead. it has a clock domain independent from the cpu clock, allowing the hdmi_cec controller to wakeup the mcu from stop mode on data reception. 3.18 controller area network (can) the can is compliant with specifications 2.0a and b (active) with a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. 3.19 universal serial bus (usb) the stm32f042x embeds a full-speed usb device peripheral compliant with the usb specification version 2.0. the internal usb phy supports usb fs signaling, embedded dp pull-up and also battery charging detection according to battery charging specification revision 1.2. the usb interface implements a full-speed (12 mbit/s) function interface with added support for usb 2.0 link power management. it has software-configurable endpoint setting with packet memory up-to 1 kb (the last 256 bytes are used for can peripheral if enabled) and suspend/resume support. it requires a precise 48 mhz clock which can be generated from the internal main pll (the clock source must use an hse crystal oscillator) or by the internal 48 mhz oscillator in automatic trimming mode. the synchronization for this oscillator can be taken from the usb data stream itself (sof signalization) which allows crystal-less operation. 3.20 clock recovery system (crs) the stm32f042x embeds a special block which allows automatic trimming of the internal 48 mhz oscillator to guarantee its optimal accuracy over the whole device operational range. this automatic trimming is based on the external synchronization signal, which could be either derived from usb sof signalization, from lse oscillator, from an external signal on crs_sync pin or generated by user software. for faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action. 3.21 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. pinouts and pin descriptions stm32f042xx 28/117 docid025832 rev 2 4 pinouts and pin descriptions figure 3. lqfp48 48-pin package pinout (top view) figure 4. ufqfpn48 48-pin package pinout (top view) / 4 ) 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 9 6 6 9 ' ' 9 ' ' , 2 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 9 % $ 7 1 5 6 7 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 3 % 3 % % 2 2 7 3 ) 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 0 6 9 3 & 3 & 2 6 & b , 1 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 3 & 2 6 & b 2 8 7 , 2 s l q v x s s o l h g e \ 9 ' ' , 2 0 6 9 8 ) 4 ) 3 1 9 % $ 7 1 5 6 7 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 & 3 & 2 6 & b , 1 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 3 & 2 6 & b 2 8 7 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 9 6 6 9 ' ' 9 ' ' , 2 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 9 ' ' 9 6 6 3 % 3 % % 2 2 7 3 ) 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 3 $ , 2 s l q v x s s o l h g e \ 9 ' ' , 2 docid025832 rev 2 29/117 stm32f042xx pinouts and pin descriptions 40 figure 5. wlcsp36 36-pin package ball-out figure 6. lqfp32 32-pin package pinout (top view) 0 6 y 9 3 & 3 & 3 & 9 6 6 3 % 3 $ 9 ' ' 3 ) 3 ) 1 5 6 7 9 ' ' $ 3 $ 3 % % 2 2 7 3 % 3 % 3 $ 3 $ 3 $ 3 % 3 % 3 $ 3 $ 3 $ 3 % 3 $ 3 $ 3 $ 3 % 3 $ 3 % 3 $ 3 $ 3 $ 3 $ 9 ' ' , 2 9 6 6 $ % & ' ( ) , 2 s l q v x s s o l h g e \ 9 ' ' , 2 0 6 9 / 4 ) 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 1 5 6 7 9 ' ' $ 3 $ 3 $ 3 $ 9 6 6 % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 % 3 $ 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 9 ' ' , 2 , 2 s l q v x s s o l h g e \ 9 ' ' , 2 pinouts and pin descriptions stm32f042xx 30/117 docid025832 rev 2 figure 7. ufqfpn32 32-pin package pinout (top view) figure 8. uqfpn28 28-pin package (top view) 1. pin pair pa11/12 can be remapped instead of pin pair pa9/10 using the syscfg_cfgr1 register. 3 $ 9 ' ' 1 5 6 7 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 $ 9 ' ' , 2 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % % 2 2 7 3 ) 3 % 3 % 3 % 0 6 9 9 ' ' $ 3 % 3 % 3 $ 3 % 3 % 3 $ 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 3 $ 9 6 6 9 6 6 $ , 2 s l q v x s s o l h g e \ 9 ' ' , 2 3 $ 3 $ 3 $ 3 % 3 $ 3 $ 3 $ % 2 2 7 3 % 9 ' ' 9 6 6 3 % 3 $ 3 % 3 % 3 $ 3 $ 3 % 3 % 0 6 9 3 $ 3 $ 9 ' ' , 2 3 $ > 3 $ @ 3 $ > 3 $ @ 3 % 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ , 2 s l q v x s s o l h g e \ 9 ' ' , 2 docid025832 rev 2 31/117 stm32f042xx pinouts and pin descriptions 40 figure 9. tssop20 20-pin package (top view) 1. pin pair pa11/12 can be remapped instead of pin pair pa9/10 using the syscfg_cfgr1 register. 0 6 9 3 ) 2 6 & b , 1 % 2 2 7 3 % 3 ) 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ 3 $ 9 ' ' 3 $ 3 $ 3 $ 3 % 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ > 3 $ @ 3 $ > 3 $ @ pinouts and pin descriptions stm32f042xx 32/117 docid025832 rev 2 table 12. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3 v i/o rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset. pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers docid025832 rev 2 33/117 stm32f042xx pinouts and pin descriptions 40 table 13. stm32f042x pin definitions pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp48/ufqfpn48 wlcsp36 lqfp32 ufqfpn32 ufqfpn28 tsspop20 alternate function additional functions 1 - - - - - vbat s - - backup power supply 2 a6 - - - - pc13 i/o tc (1) (2) - wkup2, rtc_tamp1, rtc_ts, rtc_out 3b6 - - - - pc14- osc32_in (pc14) i/o tc (1) (2) - osc32_in 4c6 - - - - pc15- osc32_out (pc15) i/o tc (1) (2) - osc32_out 5b52 2 2 2 pf0-osc_in (pf0) i/o ftf - crs_ sync i2c1_sda osc_in 6c53 3 3 3 pf1-osc_out (pf1) i/o ftf - i2c1_scl osc_out 7 d5 4 4 4 4 nrst i/o rst - device reset input / internal reset output (active low) 8 d6 32 0 16 15 vssa s - analog ground 9e55 5 5 5 vdda s - analog power supply 10 f6 6 6 6 6 pa0 i/o tta - usart2_cts, tim2_ch1_etr, tsc_g1_io1 rtc_ tamp2, wkup1, adc_in0, 11 d4 7 7 7 7 pa1 i/o tta - usart2_rts, tim2_ch2, tsc_g1_io2, eventout adc_in1 12 e4 8 8 8 8 pa2 i/o tta - usart2_tx, tim2_ch3, tsc_g1_io3 adc_in2, wkup4 13 f5 9 9 9 9 pa3 i/o tta - usart2_rx, tim2_ch4, tsc_g1_io4 adc_in3 pinouts and pin descriptions stm32f042xx 34/117 docid025832 rev 2 14 c3 10 10 10 10 pa4 i/o tta - spi1_nss, i2s1_ws, tim14_ch1, tsc_g2_io1, usart2_ck usb_noe adc_in4 15 d3 11 11 11 11 pa5 i/o tta - spi1_sck, i2s1_ck, cec, tim2_ch1_etr, tsc_g2_io2 adc_in5 16 e3 12 12 12 12 pa6 i/o tta - spi1_miso, i2s1_mck, tim3_ch1, tim1_bkin, tim16_ch1, tsc_g2_io3, eventout adc_in6 17 f4 13 13 13 13 pa7 i/o tta - spi1_mosi, i2s1_sd, tim3_ch2, tim14_ch1, tim1_ch1n, tim17_ch1, tsc_g2_io4, eventout adc_in7 18 f3 14 14 14 - pb0 i/o tta - tim3_ch3, tim1_ch2n, tsc_g3_io2, eventout adc_in8 19 f2 15 15 15 14 pb1 i/o tta - tim3_ch4, tim14_ch1, tim1_ch3n, tsc_g3_io3 adc_in9 20 d2 - 16 - - pb2 i/o ft - tsc_g3_io4 - 21 - - - - - pb10 i/o ftf - spi2_sck, cec, tsc_sync, tim2_ch3, i2c1_scl - 22 - - - - - pb11 i/o ftf - tim2_ch4, eventout, i2c1_sda - 23 f1 16 0 16 15 vss s - - ground 24 - - - 17 16 vdd s - - digital power supply 25 - - - - - pb12 i/o ft - tim1_bkin, spi2_nss, eventout - table 13. stm32f042x pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp48/ufqfpn48 wlcsp36 lqfp32 ufqfpn32 ufqfpn28 tsspop20 alternate function additional functions docid025832 rev 2 35/117 stm32f042xx pinouts and pin descriptions 40 26 - - - - - pb13 i/o ftf - spi2_sck, tim1_ch1n, i2c1_scl - 27 - - - - - pb14 i/o ftf - spi2_miso, tim1_ch2n, i2c1_sda - 28 - - - - - pb15 i/o ft - spi2_mosi, tim1_ch3n wkup7, rtc_refin 29 e2 18 18 - - pa8 i/o ft (3) usart1_ck, tim1_ch1, eventout, mco, crs_sync - 30 d1 19 19 19 17 pa9 i/o ftf (3) usart1_tx, tim1_ch2, tsc_g4_io1, i2c1_scl - 31 c1 20 20 20 18 pa10 i/o ftf (3) usart1_rx, tim1_ch3, tim17_bkin, tsc_g4_io2, i2c1_sda - 32 c2 21 21 19 (4) 17 (4) pa11 i/o ftf (3) can_rx, usart1_cts, tim1_ch4, comp1_out, tsc_g4_io3, eventout, i2c1_scl usb_dm 33 a1 22 22 20 (4) 18 (4) pa12 i/o ftf (3) can_tx,usart1_rts, tim1_etr, tsc_g4_io4, eventout, i2c1_sda usb_dp 34 b1 23 23 21 19 pa13 i/o ft (3) (5) ir_out, swdio usb_noe - 35 - - - - - vss s - - ground 36 e1 17 17 18 16 vddio2 s - - digital power supply table 13. stm32f042x pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp48/ufqfpn48 wlcsp36 lqfp32 ufqfpn32 ufqfpn28 tsspop20 alternate function additional functions pinouts and pin descriptions stm32f042xx 36/117 docid025832 rev 2 37 b2 24 24 22 20 pa14 i/o ft (3) (5) usart2_tx, swclk - 38 a2 25 25 23 - pa15 i/o ft (3) spi1_nss, i2s1_ws, usart2_rx, tim2_ch1_etr, eventout, usb_noe - 39 b3 26 26 24 - pb3 i/o ft - spi1_sck, i2s1_ck, tim2_ch2, tsc_g5_io1, eventout - 40 a3 27 27 25 - pb4 i/o ft - spi1_miso, i2s1_mck, tim17_bkin, tim3_ch1, tsc_g5_io2, eventout - 41 e6 28 28 26 - pb5 i/o ft - spi1_mosi, i2s1_sd, i2c1_smba, tim16_bkin, tim3_ch2 wkup6 42 c4 29 29 27 - pb6 i/o ftf - i2c1_scl, usart1_tx, tim16_ch1n, tsc_g5_i03 - 43 a4 30 30 28 - pb7 i/o ftf - i2c1_sda, usart1_rx, usart4_cts, tim17_ch1n, tsc_g5_io4 - 44 - - 31 - - pf11 boot0 i/o ft - - boot memory selection -b431- 1 1 pb8 boot0 i/o ftf - i2c1_scl, cec, tim16_ch1, tsc_sync, can_rx boot memory selection 45 - - 32 - - pb8 i/o ftf - i2c1_scl, cec, tim16_ch1, tsc_sync, can_rx - table 13. stm32f042x pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp48/ufqfpn48 wlcsp36 lqfp32 ufqfpn32 ufqfpn28 tsspop20 alternate function additional functions docid025832 rev 2 37/117 stm32f042xx pinouts and pin descriptions 40 46 - - - - - pb9 i/o ftf - spi2_nss, i2c1_sda, ir_out, tim17_ch1, eventout, can_tx - 47 - 32 0 - - vss s - - ground 48 a5 1 1 - - vdd s - - digital power supply 1. pc13, pc14 and pc15 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these gpios must not be used as current sources (e.g. to drive an led). 2. after the first rtc domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the rtc registers which are not reset by the system reset. for details on how to manage these gpios, refer to the rtc domain and rtc register descriptions in the reference manual. 3. pa8, pa9, pa10, pa11, pa12, pa13, pa14 and pa15 i/os are supplied by vddio2. 4. pin pair pa11/12 can be remapped instead of pin pair pa9/10 using syscfg_cfgr1 register. 5. after reset, these pins are configured as swdio and swclk alternate functions, and the internal pull-up on the swdio pin and the internal pull-down on the swclk pin are activated. table 13. stm32f042x pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp48/ufqfpn48 wlcsp36 lqfp32 ufqfpn32 ufqfpn28 tsspop20 alternate function additional functions pinouts and pin descriptions stm32f042xx 38/117 docid025832 rev 2 table 14. alternate functions selected through gpioa_afr registers for port a pin name af0 af1 af2 af3 af4 af5 af6 af7 pa0 - usart2_cts tim2_ch1_etr tsc_g1_io1 - - - - pa1 eventout usart2_rts tim2_ch2 tsc_g1_io2 - - - - pa2 - usart2_tx tim2_ch3 tsc_g1_io3 - - - - pa3 - usart2_rx tim2_ch4 tsc_g1_io4 - - - - pa4 spi1_nss, i2s1_ws usart2_ck usb_noe tsc_g2_io1 tim14_ch1 - - - pa5 spi1_sck, i2s1_ck cec tim2_ch1_etr tsc_g2_io2 - - - - pa6 spi1_miso, i2s1_mck tim3_ch1 tim1_bkin tsc_g2_io3 - tim16_ch1 eventout - pa7 spi1_mosi, i2s1_sd tim3_ch2 tim1_ch1n tsc_g2_io4 tim14_ch1 tim17_ch1 eventout - pa8 mco usart1_ck tim1_ch1 eventout crs_sync - - - pa9 - usart1_tx tim1_ch2 tsc_g4_io1 i2c1_scl mco - - pa10 tim17_bkin usart1_rx tim1_ch3 tsc_g4_io2 i2c1_sda - - - pa11 eventout usart1_cts tim1_ch4 tsc_g4_io3 can_rx i2c1_scl - - pa12 eventout usart1_rts tim1_etr tsc_g4_io4 can_tx i2c1_sda - - pa13 swdio ir_out usb_noe - - - - - pa14 swclk usart2_tx - - - - - - pa15 spi1_nss, i2s1_ws usart2_rx tim2_ch1_etr eventout - usb_noe - - stm32f042xx pinouts and pin descriptions docid025832 rev 2 39/117 table 15. alternate functions selected through gpiob_afr registers for port b pin name af0 af1 af2 af3 af4 af5 pb0 eventout tim3_ch3 tim1_ch2n tsc_g3_io2 - - pb1 tim14_ch1 tim3_ch4 tim1_ch3n tsc_g3_io3 - - pb2 - - - tsc_g3_io4 - - pb3 spi1_sck, i2s1_ck eventout tim2_ch2 tsc_g5_io1 - - pb4 spi1_miso, i2s1_mck tim3_ch1 eventout tsc_g5_io2 - tim17_bkin pb5 spi1_mosi, i2s1_sd tim3_ch2 tim16_bkin i2c1_smba - - pb6 usart1_tx i2c1_scl tim16_ch1n tsc_g5_io3 - - pb7 usart1_rx i2c1_sda tim17_ch1n tsc_g5_io4 - - pb8 cec i2c1_scl tim16_ch1 tsc_sync can_rx - pb9 ir_out i2c1_sda tim17_ch1 eventout can_tx spi2_nss pb10 cec i2c1_scl tim2_ch3 tsc_sync - spi2_sck pb11 eventout i2c1_sda tim2_ch4 - - - pb12 spi2_nss eventout tim1_bkin - - - pb13 spi2_sck - tim1_ch1n - - i2c2_scl pb14 spi2_miso - tim1_ch2n - - i2c2_sda pb15 spi2_mosi - tim1_ch3n - - - pinouts and pin descriptions stm32f042xx 40/117 docid025832 rev 2 table 16. alternate functions selected through gpiof_afr registers for port f pin name af0 af1 pf0 crs_sync i2c1_sda pf1 - i2c1_scl docid025832 rev 2 41/117 stm32f042xx memory mapping 43 5 memory mapping figure 10. stm32f042x memory map 0 6 9 5 h v h u y h g $ + % [ ) ) ) ) ) ) ) ) 3 h u l s k h u d o v 6 5 $ 0 ) o d v k p h p r u \ 5 h v h u y h g 6 \ v w h p p h p r u \ 2 s w l r q e \ w h v [ ( ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q % 2 2 7 f r q i l j x u d w l r q [ [ ( [ & [ $ [ [ [ [ [ [ [ [ ) ) ) & [ ) ) ) ) [ ) ) ) ) ) ) ) [ 5 h v h u y h g & 2 ' ( $ 3 % $ 3 % 5 h v h u y h g [ [ [ [ 5 h v h u y h g [ $ + % [ 5 h v h u y h g [ ) ) [ ) ) & r u w h [ 0 l q w h u q d o s h u l s k h u d o v memory mapping stm32f042xx 42/117 docid025832 rev 2 table 17. stm32f042x peripheral register boundary addresses bus boundary address size peripheral 0x4800 1800 - 0x5fff ffff ~384 mb reserved ahb2 0x4800 1400 - 0x4800 17ff 1 kb gpiof 0x4800 0c00 - 0x4800 13ff 2 kb reserved 0x4800 0800 - 0x4800 0bff 1 kb gpioc 0x4800 0400 - 0x4800 07ff 1 kb gpiob 0x4800 0000 - 0x4800 03ff 1 kb gpioa 0x4002 4400 - 0x47ff ffff ~128 mb reserved ahb1 0x4002 4000 - 0x4002 43ff 1 kb tsc 0x4002 3400 - 0x4002 3fff 3 kb reserved 0x4002 3000 - 0x4002 33ff 1 kb crc 0x4002 2400 - 0x4002 2fff 3 kb reserved 0x4002 2000 - 0x4002 23ff 1 kb flash interface 0x4002 1400 - 0x4002 1fff 3 kb reserved 0x4002 1000 - 0x4002 13ff 1 kb rcc 0x4002 0400 - 0x4002 0fff 3 kb reserved 0x4002 0000 - 0x4002 03ff 1 kb dma 0x4001 8000 - 0x4001 ffff 32 kb reserved apb 0x4001 5c00 - 0x4001 7fff 9 kb reserved 0x4001 5800 - 0x4001 5bff 1 kb dbgmcu 0x4001 4c00 - 0x4001 57ff 3 kb reserved 0x4001 4800 - 0x4001 4bff 1 kb tim17 0x4001 4400 - 0x4001 47ff 1 kb tim16 0x4001 3c00 - 0x4001 43ff 2 kb reserved 0x4001 3800 - 0x4001 3bff 1 kb usart1 0x4001 3400 - 0x4001 37ff 1 kb reserved 0x4001 3000 - 0x4001 33ff 1 kb spi1/i2s1 0x4001 2c00 - 0x4001 2fff 1 kb tim1 0x4001 2800 - 0x4001 2bff 1 kb reserved 0x4001 2400 - 0x4001 27ff 1 kb adc 0x4001 0800 - 0x4001 23ff 7 kb reserved 0x4001 0400 - 0x4001 07ff 1 kb exti 0x4001 0000 - 0x4001 03ff 1 kb syscfg + comp 0x4000 8000 - 0x4000 ffff 32 kb reserved docid025832 rev 2 43/117 stm32f042xx memory mapping 43 apb 0x4000 7c00 - 0x4000 7fff 1 kb reserved 0x4000 7800 - 0x4000 7bff 1 kb cec 0x4000 7400 - 0x4000 77ff 1 kb reserved 0x4000 7000 - 0x4000 73ff 1 kb pwr 0x4000 6c00 - 0x4000 6fff 1 kb crs 0x4000 6800 - 0x4000 6bff0 1 kb reserved 0x4000 6400 - 0x4000 67ff 1 kb bxcan 0x4000 6000 - 0x4000 63ff 1 kb usb/can ram 0x4000 5c00 - 0x4000 5fff 1 kb usb 0x4000 5800 - 0x4000 5bff 1 kb reserved 0x4000 5400 - 0x4000 57ff 1 kb i2c1 0x4000 4800 - 0x4000 53ff 3 kb reserved 0x4000 4400 - 0x4000 47ff 1 kb usart2 0x4000 3c00 - 0x4000 43ff 2 kb reserved 0x4000 3800 - 0x4000 3bff 1 kb spi2 0x4000 3400 - 0x4000 37ff 1 kb reserved 0x4000 3000 - 0x4000 33ff 1 kb iwdg 0x4000 2c00 - 0x4000 2fff 1 kb wwdg 0x4000 2800 - 0x4000 2bff 1 kb rtc 0x4000 2400 - 0x4000 27ff 1 kb reserved 0x4000 2000 - 0x4000 23ff 1 kb tim14 0x4000 0800 - 0x4000 1fff 6 kb reserved 0x4000 0400 - 0x4000 07ff 1 kb tim3 0x4000 0000 - 0x4000 03ff 1 kb tim2 table 17. stm32f042x peripheral register boundary addresses (continued) bus boundary address size peripheral electrical characteristics stm32f042xx 44/117 docid025832 rev 2 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ? ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ? ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 11 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 12 . figure 11. pin loading conditions figure 12. pin input voltage 0 6 9 & s ) 0 & 8 s l q 0 6 9 0 & 8 s l q 9 , 1 docid025832 rev 2 45/117 stm32f042xx electrical characteristics 94 6.1.6 power supply scheme figure 13. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 9 ' ' , 2 9 ' ' 0 6 y 9 / h y h o v k l i w h u , 2 o r j l f . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v % d f n x s f l u f x l w u \ / 6 ( 5 7 & % d f n x s u h j l v w h u v , 1 2 8 7 5 h j x o d w r u * 3 , 2 v 9 , 1 2 8 7 * 3 , 2 v [ q ) [ ? ) q ) / h y h o v k l i w h u , 2 o r j l f ? ) 9 ' ' , 2 9 6 6 [ 9 6 6 [ 9 ' ' 9 % $ 7 9 & 2 5 ( 3 r z h u v z l w f k 9 ' ' , 2 9 ' ' , 2 $ ' & $ q d o r j 5 & v 3 / / ? 9 5 ( ) 9 5 ( ) 9 ' ' $ q ) ? ) 9 ' ' $ 9 6 6 $ electrical characteristics stm32f042xx 46/117 docid025832 rev 2 6.1.7 current consumption measurement figure 14. current consumption measurement scheme 0 6 9 9 % $ 7 9 ' ' 9 ' ' $ , ' ' , ' ' $ , ' ' b 9 % $ 7 9 ' ' , 2 docid025832 rev 2 47/117 stm32f042xx electrical characteristics 94 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 18: voltage characteristics , table 19: current characteristics and table 20: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 18. voltage characteristics (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. symbol ratings min max unit v dd ?v ss external main supply voltage -0.3 4.0 v v ddio2 ?v ss external i/o supply voltage -0.3 4.0 v v dda ?v ss external analog supply voltage -0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda - 0.4 v v bat ?v ss external backup supply voltage -0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 19: current characteristics for the maximum allowed injected current values. input voltage on ft and ftf pins v ss ? 0.3 v ddiox + 4.0 v input voltage on tta pins v ss ? 0.3 4.0 v input voltage on any other pin v ss ?? 0.3 4.0 v | ? v ddx | variations between different v dd power pins - 50 mv |v ssx ?? v ss | variations between all the different ground pins -50mv v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics electrical characteristics stm32f042xx 48/117 docid025832 rev 2 table 19. current characteristics symbol ratings max. unit ? i vdd total current into sum of all vdd power lines (source) (1) 120 ma ? i vss total current out of sum of all vss ground lines (sink) (1) -120 i vdd(pin) maximum current into each vdd power pin (source) (1) 100 i vss(pin) maximum current out of each vss ground pin (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin -25 ? i io(pin) total output current sunk by sum of all i/os and control pins (2) 80 total output current sourced by sum of all i/os and control pins (2) -80 total output current sourced by sum of all i/os supplied by vddio2 -40 i inj(pin) (3) injected current on ft and ftf pins -5/+0 (4) injected current on tc and rst pin 5 injected current on tta pins (5) 5 ? i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (vdd, vdda) and ground (vss, vssa) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count qfp packages. 3. a positive injection is induced by v in > v ddiox while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 18: voltage characteristics for the maximum allowed input voltage values. 4. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 5. on these i/os, a positive injection is induced by v in > v dda . negative injection disturbs the analog performance of the device. see note (2) below table 56: adc accuracy . 6. when several inputs are submitted to a current injection, the maximum ? i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 20. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c docid025832 rev 2 49/117 stm32f042xx electrical characteristics 94 6.3 operating conditions 6.3.1 general operating conditions table 21. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency 0 48 mhz f pclk internal apb clock frequency 0 48 v dd standard operating voltage 2.0 3.6 v v ddio2 i/o supply voltage must not be supplied if v dd is not present 1.65 3.6 v v dda analog operating voltage (adc not used) must have a potential equal to or higher than v dd v dd 3.6 v analog operating voltage (adc used) 2.4 3.6 v bat backup operating voltage 1.65 3.6 v v in i/o input voltage tc and rst i/o -0.3 v ddiox +0.3 v tta i/o -0.3 v dda +0.3 ft and ftf i/o -0.3 5.5 (1) p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (2) lqfp48 - 364 mw ufqfpn48 - 606 wlcsp36 - 313 lqfp32 - 351 ufqfpn32 - 526 ufqfpn28 - 170 tssop20 - 263 t a ambient temperature for the suffix 6 version maximum power dissipation ?40 85 c low power dissipation (3) ?40 105 ambient temperature for the suffix 7 version maximum power dissipation ?40 105 c low power dissipation (3) ?40 125 t j junction temperature range suffix 6 version ?40 105 c suffix 7 version ?40 125 1. to sustain a voltage higher than v ddiox +0.3 v, the internal pull-up/pull-down resistors must be disabled. 2. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . see section 7.2: thermal characteristics . 3. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.2: thermal characteristics ). electrical characteristics stm32f042xx 50/117 docid025832 rev 2 6.3.2 operating conditions at power-up / power-down the parameters given in table 22 are derived from tests performed under the ambient temperature condition summarized in table 21 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 23 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . table 22. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate - 0 ? s/v v dd fall time rate 20 ? t vdda v dda rise time rate - 0 ? v dda fall time rate 20 ? table 23. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in the option bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.80 1.88 1.96 (3) 3. data based on characterization results, not tested in production. v rising edge 1.84 (3) 1.92 2.00 v v pdrhyst pdr hysteresis - 40 - mv t rsttempo (4) 4. guaranteed by design, not tested in production. reset temporization 1.50 2.50 4.50 ms table 24. programmable voltage detector characteristics symbol parameter conditions min typ max unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 v falling edge 2.09 2.18 2.27 v v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 v falling edge 2.18 2.28 2.38 v v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 v falling edge 2.28 2.38 2.48 v docid025832 rev 2 51/117 stm32f042xx electrical characteristics 94 6.3.4 embedded reference voltage the parameters given in table 25 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 v falling edge 2.37 2.48 2.59 v v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 v falling edge 2.47 2.58 2.69 v v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 v falling edge 2.56 2.68 2.8 v v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 v falling edge 2.66 2.78 2.9 v v pvdhyst (1) pvd hysteresis - 100 - mv i dd(pvd) pvd current consumption - 0.15 0.26 (1) a 1. guaranteed by design, not tested in production. table 24. programmable voltage detector characteristics (continued) symbol parameter conditions min typ max unit table 25. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.2 1.25 v ?40 c < t a < +85 c 1.16 1.2 1.24 (1) 1. data based on characterization results, not tested in production. v t s_vrefint adc sampling time when reading the internal reference voltage 4 (2) 2. guaranteed by design, not tested in production. -- s ? v refint internal reference voltage spread over the temperature range v dda = 3 v - - 10 (2) mv t coeff temperature coefficient - 100 (2) - 100 (2) ppm/c electrical characteristics stm32f042xx 52/117 docid025832 rev 2 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 14: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input mode ? all peripherals are disabled except when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled f pclk = f hclk the parameters given in table 26 to table 30 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . table 26. typical and maximum current consumption from v dd supply at v dd = 3.6 v symbol parameter conditions f hclk all peripherals enabled (1) all peripherals disabled unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, code executing from flash hsi48 48 mhz 20.3 23.2 23.4 24.6 12.7 14.4 14.4 14.7 ma hse bypass, pll on 48 mhz 20.2 22.9 23.0 23.9 12.6 14.1 14.3 14.4 32 mhz 14.0 16.0 16.1 16.7 8.7 9.5 9.7 10.3 24 mhz 11.0 13.5 13.7 13.8 6.9 7.6 7.8 8.2 hse bypass, pll off 8 mhz 3.9 5.2 5.3 5.6 2.6 3.1 3.2 3.3 1 mhz 0.9 1.3 1.5 1.8 0.7 1.0 1.1 1.3 hsi clock, pll on 48 mhz 20.5 23.1 23.3 23.6 12.8 14.6 14.6 15.0 32 mhz 14.3 15.6 15.9 17.0 8.6 9.5 9.7 10.0 24 mhz 11.2 13.6 13.8 14.8 6.9 7.4 7.5 7.7 hsi clock, pll off 8 mhz 4.1 5.2 5.3 5.6 2.6 3.1 3.1 3.3 docid025832 rev 2 53/117 stm32f042xx electrical characteristics 94 i dd supply current in run mode, code executing from ram hsi48 48 mhz 19.3 21.9 22.1 23.7 11.9 13.4 13.6 13.7 ma hse bypass, pll on 48 mhz 19.2 21.8 (3) 22.0 22.1 (3) 11.7 13.3 (3) 13.5 13.7 (3) 32 mhz 13.4 15.8 15.9 16.0 7.9 8.8 8.9 9.7 24 mhz 10.3 12.6 13.0 13.4 6.2 8.0 8.2 8.3 hse bypass, pll off 8 mhz 3.6 4.1 4.3 4.4 2.0 2.1 2.1 2.5 1 mhz 0.8 0.9 0.9 1.1 0.4 0.5 0.6 0.8 hsi clock, pll on 48 mhz 19.5 22.0 22.1 22.5 11.8 13.6 13.8 13.9 32 mhz 13.5 16.3 16.4 16.6 8.0 8.8 9.1 9.9 24 mhz 10.5 12.8 13.0 13.8 6.5 8.0 8.1 8.4 hsi clock, pll off 8 mhz 3.7 4.7 5.0 5.3 2.1 2.3 2.4 3.0 supply current in sleep mode, code executing from flash or ram hsi48 48 mhz 12.4 15.1 16.3 16.7 3.0 3.2 3.3 3.4 hse bypass, pll on 48 mhz 12.3 15.0 (3) 16.0 16.2 (3) 2.9 3.2 (3) 3.3 3.4 (3) 32 mhz 8.5 10.6 11.2 11.7 1.9 2.1 2.2 2.5 24 mhz 6.5 8.1 8.5 8.7 1.6 1.8 1.8 1.9 hse bypass, pll off 8 mhz 2.3 3.0 3.1 3.2 0.7 0.8 0.8 0.9 1 mhz 0.4 0.4 0.4 0.6 0.1 0.3 0.3 0.4 hsi clock, pll on 48 mhz 12.4 15.3 15.7 15.9 3.0 3.0 3.2 3.4 32 mhz 8.6 10.7 11.3 11.6 2.1 2.2 2.2 2.5 24 mhz 6.6 8.4 8.7 8.9 1.6 1.6 1.7 1.9 hsi clock, pll off 8 mhz 2.4 3.2 3.4 3.6 0.6 0.8 0.9 1.0 1. usb is kept disabled as this ip functions only with a 48 mhz clock. 2. data based on characterization results, not tested in production unless otherwise specified. 3. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ). table 26. typical and maximum current consumption from v dd supply at v dd = 3.6 v (continued) symbol parameter conditions f hclk all peripherals enabled (1) all peripherals disabled unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c electrical characteristics stm32f042xx 54/117 docid025832 rev 2 table 27. typical and maximum current consumption from the v dda supply symbol para- meter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run or sleep mode, code executing from flash or ram hsi48 48 mhz 309 325 332 342 317 334 338 344 a hse bypass, pll on 48 mhz 148 167 (3) 176 179 (3) 161 181 (3) 193 197 (3) 32 mhz 102 119 124 126 111 128 135 137 24 mhz 80 95 99 100 88 102 106 108 hse bypass, pll off 8 mhz 2.7 3.7 4.2 4.5 3.5 4.7 5.2 5.5 1 mhz 2.7 3.7 4.2 4.2 3.6 4.7 5.2 5.5 hsi clock, pll on 48 mhz 220 242 251 254 242 264 275 279 32 mhz 173 193 200 202 191 211 219 221 24 mhz 151 169 175 177 167 184 191 193 hsi clock, pll off 8 mhz 72 82 85 85 82 92 95 95 1. current consumption from the v dda supply is independent of whether the digital peripherals are enabled or disabled, being in run or sleep mode or executing from flash or ram. furthermore, when the pll is off, i dda is independent from the frequency. 2. data based on characterization results, not tested in production unless otherwise specified. 3. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ). docid025832 rev 2 55/117 stm32f042xx electrical characteristics 94 table 28. typical and maximum consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd = v dda ) max (1) unit = 2.0 v = 2.4 v = 2.7 v = 3.0 v = 3.3 v = 3.6 v t a = 25c t a = 85c t a = 105c i dd supply current in stop mode regulator in stop mode, all oscillators off 14.3 14.5 14.6 14.7 14.8 14.9 21.0 47.0 64.0 a regulator in low- power mode, all oscillators off 2.9 3.1 3.2 3.3 3.4 3.5 6.5 32.0 44.0 supply current in standby mode lsi on and iwdg on 0.8 0.9 1.1 1.2 1.3 1.5 - - - lsi off and iwdg off 0.6 0.7 0.8 0.9 1.0 1.1 2.0 2.5 3.0 i dda supply current in stop mode v dda monitoring on regulator in stop mode, all oscillators off 2.0 2.1 2.2 2.4 2.5 2.7 3.5 3.5 4.5 regulator in low-power mode, all oscillators off 2.0 2.1 2.2 2.4 2.5 2.7 3.5 3.5 4.5 supply current in standby mode lsi on and iwdg on 2.4 2.6 2.8 3.0 3.1 3.4 - - - lsi off and iwdg off 1.9 2.0 2.1 2.3 2.4 2.5 3.4 3.5 4.5 supply current in stop mode v dda monitoring off regulator in stop mode, all oscillators off 1.3 1.3 1.3 1.4 1.4 1.5 - - - regulator in low-power mode, all oscillators off 1.3 1.3 1.3 1.4 1.4 1.5 - - - supply current in standby mode lsi on and iwdg on 1.7 1.8 1.8 2.0 2.1 2.2 - - - lsi off and iwdg off 1.1 1.2 1.2 1.3 1.3 1.4 - - - 1. data based on characterization results, not tested in production unless otherwise specified. electrical characteristics stm32f042xx 56/117 docid025832 rev 2 typical current consumption the mcu is placed under the following conditions: ? v dd = v dda = 3.3 v ? all i/o pins are in analog input configuration ? the flash access time is adjusted to f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled, f pclk = f hclk ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8 and 16 is used for the frequencies 4 mhz, 2 mhz, 1 mhz and 500 khz respectively table 29. typical and maximum current consumption from the v bat supply symbol parameter conditions typ @ v bat max (1) unit = 1.65 v = 1.8 v = 2.4 v = 2.7 v = 3.3 v = 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd _ vbat rtc domain supply current lse & rtc on; ?xtal mode?: lower driving capability; lsedrv[1:0] = '00' 0.5 0.5 0.6 0.7 0.9 1.1 1.2 1.5 2.0 a lse & rtc on; ?xtal mode? higher driving capability; lsedrv[1:0] = '11' 0.8 0.9 1.1 1.2 1.4 1.5 1.6 2.0 2.6 1. data based on characterization results, not tested in production. docid025832 rev 2 57/117 stm32f042xx electrical characteristics 94 table 30. typical current consumption, code executing from flash, running from hse 8 mhz crystal symbol parameter f hclk typical consumption in run mode typical consumption in sleep mode unit peripherals enabled peripherals disabled peripherals enabled peripherals disabled i dd current consumption from v dd supply 48 mhz 20.7 12.8 12.3 3.4 ma 36 mhz 15.9 9.9 9.5 2.7 32 mhz 14.3 9.0 8.5 2.5 24 mhz 11.0 7.1 6.6 2.1 16 mhz 7.7 5.0 4.7 1.6 8 mhz 4.3 3.0 2.7 1.2 4 mhz 2.6 2.0 1.7 0.9 2 mhz 1.8 1.5 1.2 0.8 1 mhz 1.4 1.2 1.0 0.8 500 khz 1.2 1.1 0.8 0.7 i dda current consumption from v dda supply 48 mhz 163.3 a 36 mhz 124.3 32 mhz 111.9 24 mhz 87.1 16 mhz 62.5 8 mhz 2.5 4 mhz 2.5 2 mhz 2.5 1 mhz 2.5 500 khz 2.5 electrical characteristics stm32f042xx 58/117 docid025832 rev 2 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low . the value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in table 50: i/o static characteristics. for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input value. unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently , as a result of external electromagnetic noise. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by using pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 32: peripheral current consumption), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the i/o supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: i sw v ddiox f sw c u u = where i sw is the current sunk by a switching i/o to charge/discharge the capacitive load v ddiox is the i/o supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacitance including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. docid025832 rev 2 59/117 stm32f042xx electrical characteristics 94 table 31. switching output i/o current consumption symbol parameter conditions (1) 1. c s = 7 pf (estimated value). i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v ddiox = 3.3 v c =c int 4 mhz 0.07 ma 8 mhz 0.15 16 mhz 0.31 24 mhz 0.53 48 mhz 0.92 v ddiox = 3.3 v c ext = 0 pf c = c int + c ext + c s 4 mhz 0.18 8 mhz 0.37 16 mhz 0.76 24 mhz 1.39 48 mhz 2.188 v ddiox = 3.3 v c ext = 10 pf c = c int + c ext + c s 4 mhz 0.32 8 mhz 0.64 16 mhz 1.25 24 mhz 2.23 48 mhz 4.442 v ddiox = 3.3 v c ext = 22 pf c = c int + c ext + c s 4 mhz 0.49 8 mhz 0.94 16 mhz 2.38 24 mhz 3.99 v ddiox = 3.3 v c ext = 33 pf c = c int + c ext + c s 4 mhz 0.64 8 mhz 1.25 16 mhz 3.24 24 mhz 5.02 v ddiox = 3.3 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.81 8 mhz 1.7 16 mhz 3.67 v ddiox = 2.4 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.66 8 mhz 1.43 16 mhz 2.45 24 mhz 4.97 electrical characteristics stm32f042xx 60/117 docid025832 rev 2 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in table 32 . the mcu is placed under the following conditions: ? all i/o pins are in analog mode ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature and supply voltage conditions summarized in table 18: voltage characteristics table 32. peripheral current consumption peripheral typical consumption at 25 c unit ahb busmatrix (1) 2.2 a/mhz crc 1.9 dma 5.1 flash interface 15.0 gpioa 8.2 gpiob 7.7 gpioc 2.1 gpiof 1.8 sram 1.1 tsc 4.9 all ahb peripherals 50.7 docid025832 rev 2 61/117 stm32f042xx electrical characteristics 94 apb apb-bridge (2) 2.1 a/mhz adc (3) 4.7 can 13.8 cec 2.4 crs 1.8 debug (mcu debug feature) 1.1 i2c1 4.5 pwr 2.3 spi1 9.4 spi2 6.5 syscfg 2.7 tim1 16.0 tim2 17.6 tim3 12.5 tim14 6.4 tim16 7.9 tim17 7.8 usart1 18.6 usart2 6.5 usb 6.6 wwdg 2.2 all apb peripherals 153.8 1. the busmatrix is automatically active when at least one master is on (cpu, dma). 2. the apb bridge is automatically active when at least one peripheral is on on the bus. 3. the power consumption of the analog part (i dda ) of peripherals such as adc is not included. refer to the tables of characteristics in the subsequent sections. table 32. peripheral current consumption (continued) peripheral typical consumption at 25 c unit electrical characteristics stm32f042xx 62/117 docid025832 rev 2 6.3.6 wakeup time from low-power mode the wakeup times given in table 33 are the latency between the event and the execution of the first user instruction. the device goes in low-power mode after the wfe (wait for event) instruction, in the case of a wfi (wait for interruption) instruction, 16 cpu cycles must be added to the following timings due to the interrupt latency in the cortex m0 architecture. the sysclk clock source setting is kept unchanged after wakeup from sleep mode. during wakeup from stop or standby mode, sysclk takes the default setting: hsi 8 mhz. the wakeup source from sleep and stop mode is an exti line configured in event mode. the wakeup source from standby mode is the wkup1 pin (pa0). all timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . table 33. low-power mode wakeup timings symbol parameter conditions typ @v dd = v dda max unit = 2.0 v = 2.4 v = 2.7 v = 3 v = 3.3 v t wustop wakeup from stop mode regulator in run mode 3.2 3.1 2.9 2.9 2.8 5 s regulator in low power mode 7.0 5.8 5.2 4.9 4.6 9 t wustandby wakeup from standby mode 60.4 55.6 53.5 52 51 - t wusleep wakeup from sleep mode 4 sysclk cycles - docid025832 rev 2 63/117 stm32f042xx electrical characteristics 94 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 15: high-speed external clock source ac timing diagram . figure 15. high-speed external clock source ac timing diagram table 34. high-speed external user clock characteristics symbol parameter (1) conditions min typ max unit f hse_ext user external clock source frequency - - 8 32 mhz v hseh osc_in input pin high level voltage - 0.7 v ddiox -v ddiox v v hsel osc_in input pin low level voltage - v ss - 0.3 v ddiox t w(hseh) t w(hsel) osc_in high or low time - 15 - - ns t r(hse) t f(hse) osc_in rise or fall time - - - 20 1. guaranteed by design, not tested in production. 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / electrical characteristics stm32f042xx 64/117 docid025832 rev 2 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 16 . figure 16. low-speed external clock source ac timing diagram table 35. low-speed external user clock characteristics symbol parameter (1) conditions min typ max unit f lse_ext user external clock source frequency - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7 v ddiox -v ddiox v v lsel osc32_in input pin low level voltage v ss - 0.3 v ddiox t w(lseh) t w(lsel) osc32_in high or low time 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 50 1. guaranteed by design, not tested in production. 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / docid025832 rev 2 65/117 stm32f042xx electrical characteristics 94 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on design simulation results obtained with typical external components specified in table 36 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 17 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the combined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 36. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. min (2) typ max (2) 2. guaranteed by design, not tested in production. unit f osc_in oscillator frequency 4 8 32 mhz r f feedback resistor - 200 - k ? i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time - 8.5 ma v dd = 3.3 v, rm = 30 ? , cl = 10 pf@8 mhz - 0.4 - v dd = 3.3 v, rm = 45 ? , cl = 10 pf@8 mhz - 0.5 - v dd = 3.3 v, rm = 30 ? , cl = 5 pf@32 mhz - 0.8 - v dd = 3.3 v, rm = 30 ? , cl = 10 pf@32 mhz -1- v dd = 3.3 v, rm = 30 ? , cl = 20 pf@32 mhz - 1.5 - g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms electrical characteristics stm32f042xx 66/117 docid025832 rev 2 figure 17. typical application with an 8 mhz crystal 1. r ext value depends on the crystal characteristics. 0 6 9 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q 5 ( ; 7 & / & / 2 6 & b , 1 2 6 & b 2 8 7 5 ) i + 6 ( docid025832 rev 2 67/117 stm32f042xx electrical characteristics 94 low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information given in this paragraph are based on design simulation results obtained with typical external components specified in table 37 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 37. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability - 0.5 0.9 a lsedrv[1:0]= 01 medium low driving capability --1 lsedrv[1:0] = 10 medium high driving capability - - 1.3 lsedrv[1:0]=11 higher driving capability - - 1.6 g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]= 01 medium low driving capability 8- - lsedrv[1:0] = 10 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) startup time v ddiox is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer electrical characteristics stm32f042xx 68/117 docid025832 rev 2 figure 18. typical application with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 0 6 9 2 6 & b 2 8 7 2 6 & b , 1 i / 6 ( & / n + ] u h v r q d w r u & / 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v ' u l y h s u r j u d p p d e o h d p s o l i l h u docid025832 rev 2 69/117 stm32f042xx electrical characteristics 94 6.3.8 internal clock source characteristics the parameters given in table 38 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . the provided curves are characterization results, not tested in production. high-speed internal (hsi) rc oscillator figure 19. hsi oscillator accuracy characterization results table 38. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 8 - mhz trim hsi user trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) t a = ?40 to 105 c ?3.8 (3) 3. data based on characterization results, not tested in production. - 4.6 (3) % t a = ?10 to 85 c ?2.9 (3) - 2.9 (3) % t a = 0 to 70 c ?2.3 (3) - 2.2 (3) % t a = 25 c ?1 - 1 % t su(hsi) hsi oscillator startup time 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption - 80 100 (2) a - 3 6 - ! 8 - ) . 4 ; ? # = ! electrical characteristics stm32f042xx 70/117 docid025832 rev 2 high-speed internal 14 mhz (hsi14) rc oscillator (dedicated to adc) figure 20. hsi14 oscillator accuracy characterization results table 39. hsi14 oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi14 frequency - 14 - mhz trim hsi14 user-trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi14) duty cycle 45 (2) -55 (2) % acc hsi14 accuracy of the hsi14 oscillator (factory calibrated) t a = ?40 to 105 c ?4.2 (3) 3. data based on characterization results, not tested in production. - 5.1 (3) % t a = ?10 to 85 c ?3.2 (3) - 3.1 (3) % t a = 0 to 70 c ?2.5 (3) - 2.3 (3) % t a = 25 c ?1 - 1 % t su(hsi14) hsi14 oscillator startup time 1 (2) -2 (2) s i dda(hsi14) hsi14 oscillator power consumption - 100 150 (2) a - 3 6 - ! 8 - ) . 4 ; ? # = ! docid025832 rev 2 71/117 stm32f042xx electrical characteristics 94 high-speed internal 48 mhz (hsi48) rc oscillator figure 21. hsi48 oscillator accuracy characterization results table 40. hsi48 oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi48 frequency - 48 - mhz trim hsi48 user-trimming step 0.09 (2) 0.14 0.2 (2) % ducy (hsi48) duty cycle 45 (2) 2. guaranteed by design, not tested in production. -55 (2) % acc hsi48 accuracy of the hsi48 oscillator (factory calibrated) t a = ?40 to 105 c -4.9 (3) 3. data based on characterization results, not tested in production. - 4.7 (3) % t a = ?10 to 85 c -4.1 (3) - 3.7 (3) % t a = 0 to 70 c -3.8 (3) - 3.4 (3) % t a = 25 c -2.8 - 2.9 % t su(hsi48) hsi48 oscillator startup time - - 6 (2) s i dda(hsi48) hsi48 oscillator power consumption - 312 350 (2) a - 3 6 - ! 8 - ) . 4 ; ? # = ! electrical characteristics stm32f042xx 72/117 docid025832 rev 2 low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in table 42 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . table 41. lsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dda(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a table 42. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care to use the appropriate multiplier factors to obtain pll input clock values compatible with the range defined by f pll_out . 1 (2) 8.0 24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) - 48 mhz t lock pll lock time - - 200 (2) 2. guaranteed by design, not tested in production. s jitter pll cycle-to-cycle jitter - - 300 (2) ps docid025832 rev 2 73/117 stm32f042xx electrical characteristics 94 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. 6.3.11 emc characteristics susceptibility tests are performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 45 . they are based on the ems levels and classes defined in application note an1709. table 43. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a ??? ?40 to +105 c 40 53.5 60 s t erase page (1 kb) erase time t a ?? ?40 to +105 c 20 - 40 ms t me mass erase time t a ?? ?40 to +105 c 20 - 40 ms i dd supply current write mode - - 10 ma erase mode - - 12 ma table 44. flash memory endurance and data retention symbol parameter conditions min (1) 1. data based on characterization results, not tested in production. unit n end endurance t a = ?40 to +105 c 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 electrical characteristics stm32f042xx 74/117 docid025832 rev 2 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. table 45. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd ?? 3.3 v, lqfp48, t a ?? +25 c, f hclk ?? 48 mhz, conforming to iec 61000-4-2 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd ??? 3.3 v, lqfp48, t a ?? +25c, f hclk ?? 48 mhz, conforming to iec 61000-4-4 4b table 46. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz s emi peak level v dd ?? 3.6 v, t a ?? 25 c, lqfp48 package compliant with iec 61967-2 0.1 to 30 mhz -9 db v 30 to 130 mhz 9 130 mhz to 1 ghz 17 emi level 3 - docid025832 rev 2 75/117 stm32f042xx electrical characteristics 94 6.3.12 electrical sensitivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current injection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v ddiox (for standard, 3.3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. table 47. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a ?? +25 c, conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a ?? +25 c, conforming to ansi/esd stm5.3.1 ii 500 table 48. electrical sensitivities symbol parameter conditions class lu static latch-up class t a ?? +105 c conforming to jesd78a ii level a electrical characteristics stm32f042xx 76/117 docid025832 rev 2 functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of the -5 a/+0 a range) or other functional failure (for example reset occurrence or oscillator frequency deviation). the characterization results are given in table 49 . negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 50 are derived from tests performed under the conditions summarized in table 21: general operating conditions . all i/os are designed as cmos- and ttl-compliant. table 49. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on pa12 pin -0 +5 ma injected current on pa9, pb3, pb13, pf11 pins with induced leakage current on adjacent pins less than 50 a -5 na injected current on pb0, pb1 and all other ft and ftf pins -5 na injected current on all other tc, tta and rst pins -5 +5 table 50. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v ddiox +0.07 (1) v ft and ftf i/o - - 0.475 v ddiox ?0.2 (1) all i/os - - 0.3 v ddiox v ih high level input voltage tc and tta i/o 0.445 v ddiox +0.398 (1) -- v ft and ftf i/o 0.5 v ddiox +0.2 (1) -- all i/os 0.7 v ddiox -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - docid025832 rev 2 77/117 stm32f042xx electrical characteristics 94 i lkg input leakage current (2) tc, ft and ftf i/o tta in digital mode v ss ? ? v in ? ?? v ddiox -- ? ? 0.1 a tta in digital mode v ddiox ? ? v in ? ?? v dda --1 tta in analog mode v ss ? ? v in ? ?? v dda -- ? ? 0.2 ft and ftf i/o (3) v ddiox ? ?? v in ? ?? 5 v --10 r pu weak pull-up equivalent resistor (4) v in ?? v ss 25 40 55 k ? r pd weak pull-down equivalent resistor (4) v in ?? v ddiox 25 40 55 k ? c io i/o pin capacitance - 5 - pf 1. data based on design simulation only. not tested in production. 2. the leakage could be higher than the maximum value, if negative current is injected on adjacent pins. refer to table 49: i/o current injection susceptibility . 3. to sustain a voltage higher than v ddiox + 0.3 v, the internal pull-up/pull-down resistors must be disabled. 4. pull-up and pull-down resistors are designed with a true resistance in series with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimal (~10% order). table 50. i/o static characteristics (continued) symbol parameter conditions min typ max unit electrical characteristics stm32f042xx 78/117 docid025832 rev 2 all i/os are cmos- and ttl-compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 22 for standard i/os, and in figure 23 for 5 v tolerant i/os. the following curves are design simulation results, not tested in production. figure 22. tc and tta i/o input characteristics ms32130v3 0 0.5 1 1.5 2 2.5 3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 ttl standard requirement ttl standard requirement t tl stan d ar d re q uiremen t tested range tested range undefined input range v ddiox (v) v in (v) docid025832 rev 2 79/117 stm32f042xx electrical characteristics 94 figure 23. five volt tolerant (ft and ftf) i/o input characteristics 0 0.5 1 1.5 2 2.5 3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 ttl standard requirement ttl standard requirement t tl stan d ar d re q uiremen t tested range tested range v in (v) v ddiox (v) ms32131v3 electrical characteristics stm32f042xx 80/117 docid025832 rev 2 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v ddiox, plus the maximum consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating ? i vdd (see table 18: voltage characteristics ). ? the sum of the currents sunk by all the i/os on v ss , plus the maximum consumption of the mcu sunk on v ss , cannot exceed the absolute maximum rating ? i vss (see table 18: voltage characteristics ). output voltage levels unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . all i/os are cmos- and ttl-compliant (ft, tta or tc unless otherwise specified). table 51. output voltage characteristics (1) symbol parameter conditions min max unit v ol output low level voltage for an i/o pin cmos port (2) |i io | = 8 ma v ddiox ? 2.7 v - 0.4 v v oh output high level voltage for an i/o pin v ddiox ?0.4 - v ol output low level voltage for an i/o pin ttl port (2) |i io | = 8 ma v ddiox ? 2.7 v - 0.4 v v oh output high level voltage for an i/o pin 2.4 - v ol (3) output low level voltage for an i/o pin |i io | = 20 ma v ddiox ? 2.7 v - 1.3 v v oh (3) output high level voltage for an i/o pin v ddiox ?1.3 - v ol (3) output low level voltage for an i/o pin |i io | = 6 ma v ddiox ? 2 v - 0.4 v v oh (3) output high level voltage for an i/o pin v ddiox ?0.4 - v ol (3) output low level voltage for an i/o pin |i io | = 4 ma - 0.4 v v oh (3) output high level voltage for an i/o pin v ddiox ?0.4 - v v olfm+ (3) output low level voltage for an ftf i/o pin in fm+ mode |i io | = 20 ma v ddiox ? 2.7 v - 0.4 v |i io | = 10 ma - 0.4 v 1. the i io current sourced or sunk by the device must always respect the absolute maximum rating specified in table 18: voltage characteristics , and the sum of the currents sourced or sunk by all the i/os (i/o ports and control pins) must always respect the absolute maximum ratings ? i io . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. data based on characterization results. not tested in production. docid025832 rev 2 81/117 stm32f042xx electrical characteristics 94 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 24 and table 52 , respectively. unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . table 52. i/o ac characteristics (1)(2) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 2 mhz t f(io)out output fall time - 125 ns t r(io)out output rise time - 125 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 1 mhz t f(io)out output fall time - 125 ns t r(io)out output rise time - 125 01 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 10 mhz t f(io)out output fall time - 25 ns t r(io)out output rise time - 25 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 4 mhz t f(io)out output fall time - 62.5 ns t r(io)out output rise time - 62.5 11 f max(io)out maximum frequency (3) c l = 30 pf, v ddiox ? 2.7 v - 50 mhz c l = 50 pf, v ddiox ? 2.7 v - 30 c l = 50 pf, 2 v ?? v ddiox ? 2.7 v - 20 c l = 50 pf, v ddiox ? 2 v - 10 t f(io)out output fall time c l = 30 pf, v ddiox ? 2.7 v - 5 ns c l = 50 pf, v ddiox ? 2.7 v - 8 c l = 50 pf, 2 v ?? v ddiox ? 2.7 v - 12 c l = 50 pf, v ddiox ? 2 v - 25 t r(io)out output rise time c l = 30 pf, v ddiox ? 2.7 v - 5 c l = 50 pf, v ddiox ? 2.7 v - 8 c l = 50 pf, 2 v ?? v ddiox ? 2.7 v - 12 c l = 50 pf, v ddiox ? 2 v - 25 electrical characteristics stm32f042xx 82/117 docid025832 rev 2 figure 24. i/o ac characteristics definition 6.3.15 nrst pin characteristics the nrst pin input driver uses the cmos technology. it is connected to a permanent pull- up resistor, r pu . unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . fm+ configuration (4) f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 2 mhz t f(io)out output fall time - 12 ns t r(io)out output rise time - 34 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 0.5 mhz t f(io)out output fall time - 16 ns t r(io)out output rise time - 44 t extipw pulse width of external signals detected by the exti controller 10 - ns 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the stm32f0xxxx rm0091 reference manual for a description of gpio port configuration register. 2. guaranteed by design, not tested in production. 3. the maximum frequency is defined in figure 24 . 4. when fm+ configuration is set, the i/o speed control is bypassed. refer to the stm32f0xxxx reference manual rm0091 for a detailed description of fm+ i/o configuration. table 52. i/o ac characteristics (1)(2) (continued) ospeedry [1:0] value (1) symbol parameter conditions min max unit 0 6 9 7 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w w ? z k h q o r d g h g e \ & v h h w k h w d e o h , 2 $ & f k d u d f w h u l v w l f v g h i l q l w l r q u i u , 2 r x w w i , 2 r x w w - 7 d q g l i w k h g x w \ f \ f o h l v table 53. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage - - 0.3 v dd +0.07 (1) v v ih(nrst) nrst input high level voltage 0.445 v dd +0.398 (1) -- docid025832 rev 2 83/117 stm32f042xx electrical characteristics 94 figure 25. recommended nrst pin protection 1. the external capacitor protects the device against parasitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 53: nrst pin characteristics . otherwise the reset will not be taken into account by the device. 6.3.16 12-bit adc characteristics unless otherwise specified, the parameters given in table 54 are preliminary values derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions summarized in table 21: general operating conditions . note: it is recommended to perform a calibration after each power-up. v hys(nrst) nrst schmitt trigger voltage hysteresis - 200 - mv r pu weak pull-up equivalent resistor (2) v in ?? v ss 25 40 55 k ? v f(nrst) nrst input filtered pulse - - 100 (1) ns v nf(nrst) nrst input not filtered pulse 2.7 < v dd < 3.6 300 (3) -- ns 2.0 < v dd < 3.6 500 (3) -- 1. data based on design simulation only. not tested in production. 2. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is minimal (~10% order). 3. data based on design simulation only. not tested in production. table 53. nrst pin characteristics (continued) symbol parameter conditions min typ max unit 5 3 8 9 ' ' 0 6 9 , q w h u q d o u h v h w ( [ w h u q d o u h v h w f l u f x l w 1 5 6 7 ) l o w h u ? ) table 54. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on 2.4 - 3.6 v i dda (adc) current consumption of the adc (1) v dd = v dda = 3.3 v - 0.9 - ma f adc adc clock frequency 0.6 - 14 mhz f s (2) sampling rate 0.05 - 1 mhz r ain t s f adc c adc 2 n2 + ln u u ------------------------------------------------------------- - r adc ? electrical characteristics stm32f042xx 84/117 docid025832 rev 2 equation 1: r ain max formula f trig (2) external trigger frequency f adc = 14 mhz - - 823 khz - - 17 1/f adc v ain conversion voltage range 0 - v dda v r ain (2) external input impedance see equation 1 and table 55 for details - - 50 k : r adc (2) sampling switch resistance --1k : c adc (2) internal sample and hold capacitor --8pf t cal (2) calibration time f adc = 14 mhz 5.9 ?s 83 1/f adc w latency (2) adc_dr register write latency adc clock = hsi14 1.5 adc cycles + 2 f pclk cycles - 1.5 adc cycles + 3 f pclk cycles adc clock = pclk/2 - 4.5 - f pclk cycle adc clock = pclk/4 - 8.5 - f pclk cycle t latr (2) trigger conversion latency f adc = f pclk /2 = 14 mhz 0.196 ?s f adc = f pclk /2 5.5 1/f pclk f adc = f pclk /4 = 12 mhz 0.219 ?s f adc = f pclk /4 10.5 1/f pclk f adc = f hsi14 = 14 mhz 0.188 - 0.259 ?s jitter adc adc jitter on trigger conversion f adc = f hsi14 -1-1/f hsi14 t s (2) sampling time f adc = 14 mhz 0.107 - 17.1 ?s 1.5 - 239.5 1/f adc t stab (2) power-up time 0 0 1 ?s t conv (2) total conversion time (including sampling time) f adc = 14 mhz 1 - 18 ?s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. during conversion of the sampled value (12.5 x adc clock period), an additional consumption of 100 ?a on i dda and 60 ?a on i dd should be taken into account. 2. guaranteed by design, not tested in production. table 54. adc characteristics (continued) symbol parameter conditions min typ max unit docid025832 rev 2 85/117 stm32f042xx electrical characteristics 94 the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 55. r ain max for f adc = 14 mhz t s (cycles) t s ( s) r ain max (k ? ) (1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na 1. guaranteed by design, not tested in production. table 56. adc accuracy (1)(2)(3) symbol parameter test conditions typ max (4) unit et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k ? v dda = 3 v to 3.6 v t a = 25 c 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k ? v dda = 2.7 v to 3.6 v t a = ? 40 to 105 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k ? v dda = 2.4 v to 3.6 v t a = 25 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and ? i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production. electrical characteristics stm32f042xx 86/117 docid025832 rev 2 figure 26. adc accuracy characteristics figure 27. typical connection diagram using the adc 1. refer to table 54: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 13: power supply scheme . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. ( 2 ( * / 6 % , ' ( $ / ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h ( 7 7 r w d o 8 q d g m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g w k h l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h i l u v w l g h d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h ( 7 ( ' ( / 9 ' ' $ 9 6 6 $ - 3 6 0 6 9 9 ' ' $ $ , 1 [ , / ? ? $ 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 7 5 $ ' & e l w f r q y h u w h u & $ ' & 6 d p s o h d q g k r o g $ ' & f r q y h u w h u docid025832 rev 2 87/117 stm32f042xx electrical characteristics 94 6.3.17 temperature sensor characteristics 6.3.18 v bat monitoring characteristics 6.3.19 timer characteristics the parameters given in the following tables are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). table 57. ts characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - ? ? 1 ? ? 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 30 voltage at 30 c ( ?? 5 c) (2) 1.34 1.43 1.52 v t start (1) startup time 4 - 10 s t s_temp (1) adc sampling time when reading the temperature 4- - s 1. guaranteed by design, not tested in production. 2. measured at v dda = 3.3 v ?? 10 mv. the v 30 adc conversion result is stored in the ts_cal1 byte ?? refer to table 3: temperature sensor calibration values . table 58. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k ? q ratio on v bat measurement - 2 - er (1) error on q ?1 - +1 % t s_vbat (1) adc sampling time when reading the v bat 4- - s 1. guaranteed by design, not tested in production. table 59. timx characteristics symbol parameter conditions min max unit t res(tim) timer resolution time 1- t timxclk f timxclk = 48 mhz 20.8 - ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 48 mhz 0 24 mhz res tim timer resolution timx (except tim2) - 16 bit tim2 - 32 t counter 16-bit counter clock period 1 65536 t timxclk f timxclk = 48 mhz 0.0208 1365 s electrical characteristics stm32f042xx 88/117 docid025832 rev 2 6.3.20 communication interfaces i 2 c interface characteristics the i2c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i2c timings requirements are guaranteed by design when the i2c peripheral is properly configured (refer to reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v ddiox is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i2c i/os characteristics. t max_count maximum possible count with 32-bit counter - 65536 65536 t timxclk f timxclk = 48 mhz - 89.48 s table 60. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 khz clock but the microcontroller internal rc frequency can vary from 30 to 60 khz. moreover, given an exact rc oscillator frequency, the exact timings still depend on the phasing of the apb interface clock versus the lsi clock so that there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.1 409.6 ms /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 table 61. wwdg min/max timeout value at 48 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0853 5.4613 ms 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 table 59. timx characteristics (continued) symbol parameter conditions min max unit docid025832 rev 2 89/117 stm32f042xx electrical characteristics 94 all i2c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 62. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns electrical characteristics stm32f042xx 90/117 docid025832 rev 2 spi/i 2 s characteristics unless otherwise specified, the parameters given in table 63 for spi or in table 64 for i 2 s are derived from tests performed under the ambient temperature, f pclkx frequency and supply voltage conditions summarized in table 21: general operating conditions . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 63. spi characteristics (1) symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 18 mhz slave mode - 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 15 pf - 6 ns t su(nss) nss setup time slave mode 4tpclk - ns t h(nss) nss hold time slave mode 2tpclk + 10 - t w(sckh) t w(sckl) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk/2 -2 tpclk/2 + 1 t su(mi) t su(si) data input setup time master mode 4 - slave mode 5 - t h(mi) data input hold time master mode 4 - t h(si) slave mode 5 - t a(so) (2) data output access time slave mode, f pclk = 20 mhz 0 3tpclk t dis(so) (3) data output disable time slave mode 0 18 t v(so) data output valid time slave mode (after enable edge) - 22.5 t v(mo) data output valid time master mode (after enable edge) - 6 t h(so) data output hold time slave mode (after enable edge) 11.5 - t h(mo) master mode (after enable edge) 2 - ducy(sck) spi slave input clock duty cycle slave mode 25 75 % 1. data based on characterization results, not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z docid025832 rev 2 91/117 stm32f042xx electrical characteristics 94 figure 28. spi timing diagram - slave mode and cpha = 0 figure 29. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . d l f ^ < /v?? w , a d k ^ / / e w h d d / ^ k k h d w h d w , a d ^ k h d d ^ / e / d k h d > ^ / e > ^ k h d w k >a w k >a / d / e e ^ ^ ]v?? ? ^ h~ e ^ ^ ?~ ^ < ?z~ e ^ ^ ?~ ^ k ?~ ^ < ,?~ ^ < > ?~ ^ k ?z~ ^ k ??~ ^ <?(~ ^ < ?]?~ ^ k ??~ ^ / ?z~ ^ / d l ^ < /v?? w , a d k ^ / / e w h d d / ^ k k h d w h d w , a d ^ k h d d ^ / e / d k h d > ^ / e > ^ k h d w k >a w k >a / d / e ? ^ h~ e ^ ^ ? ~ ^ < ? z~ e ^ ^ ? ~ ^ k ? ~ ^ > , ? ~ ^ > > ? ~ ^ k ? z~ ^ k ? ?~ ^ > ? (~ ^ > ? ]?~ ^ k ? ?~ ^ / ? z~ ^ / e ^ ^ ]v?? electrical characteristics stm32f042xx 92/117 docid025832 rev 2 figure 30. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . a i 6 3 # + / u t p u t # 0 ( ! - / 3 ) / 5 4 0 5 4 - ) 3 / ) . 0 5 4 # 0 ( ! - 3 " ) . - 3 " / 5 4 " ) 4 ) . , 3 " / 5 4 , 3 " ) . # 0 / , # 0 / , " ) 4 / 5 4 . 3 3 i n p u t t c 3 # + t w 3 # + ( t w 3 # + , t r 3 # + t f 3 # + t h - ) ( i g h 3 # + / u t p u t # 0 ( ! # 0 ( ! # 0 / , # 0 / , t s u - ) t v - / t h - / table 64. i 2 s characteristics (1) symbol parameter conditions min max unit f ck 1/t c(ck) i 2 s clock frequency master mode (data: 16 bits, audio frequency = 48 khz) 1.597 1.601 mhz slave mode 0 6.5 t r(ck) i 2 s clock rise time capacitive load c l = 15 pf - 10 ns t f(ck) i 2 s clock fall time - 12 t w(ckh) i2s clock high time master f pclk = 16 mhz, audio frequency = 48 khz 306 - t w(ckl) i2s clock low time 312 - t v(ws) ws valid time master mode 2 - t h(ws) ws hold time master mode 2 - t su(ws) ws setup time slave mode 7 - t h(ws) ws hold time slave mode 0 - ducy(sck) i2s slave input clock duty cycle slave mode 25 75 % docid025832 rev 2 93/117 stm32f042xx electrical characteristics 94 figure 31. i2s slave timing diagram (philips protocol) 1. measurement points are done at cmos levels: 0.3 v ddiox and 0.7 v ddiox . 2. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. t su(sd_mr) data input setup time master receiver 6 - ns t su(sd_sr) data input setup time slave receiver 2 - t h(sd_mr) (2) data input hold time master receiver 4 - t h(sd_sr) (2) slave receiver 0.5 - t v(sd_st) (2) data output valid time slave transmitter (after enable edge) slave transmitter (after enable edge) master transmitter (after enable edge) master transmitter (after enable edge) - t h(sd_st) data output hold time 13 - t v(sd_mt) (2) data output valid time - 4 t h(sd_mt) data output hold time 0 - 1. data based on design simulation and/or characterization results, not tested in production. 2. depends on f pclk . for example, if f pclk = 8 mhz, then t pclk = 1/f plclk = 125 ns. table 64. i 2 s characteristics (1) (continued) symbol parameter conditions min max unit & . , q s x w & 3 2 / & 3 2 / w f & . : 6 l q s x w 6 ' w u d q v p l w 6 ' u h f h l y h w z & . + w z & . / w v x : 6 w y 6 ' b 6 7 w k 6 ' b 6 7 w k : 6 w v x 6 ' b 6 5 w k 6 ' b 6 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % w u d q v p l w d l e / 6 % u h f h l y h / 6 % w u d q v p l w electrical characteristics stm32f042xx 94/117 docid025832 rev 2 figure 32. i2s master timing diagram (philips protocol) 1. data based on characterization results, not tested in production. 2. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. can (controller area network) interface refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t docid025832 rev 2 95/117 stm32f042xx package characteristics 115 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 33. lqfp48 ? 7 mm x 7 mm, 48 pin low-profile quad flat package outline 1. drawing is not to scale. table 65. lqfp48 ? 7 mm x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + package characteristics stm32f042xx 96/117 docid025832 rev 2 figure 34. lqfp48 recommended footprint 1. dimensions are in millimeters. c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 k 0 3.5 7 0 3.5 7 1. values in inches are converted from mm and rounded to 4 decimal digits. table 65. lqfp48 ? 7 mm x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a i d docid025832 rev 2 97/117 stm32f042xx package characteristics 115 marking of engineering samples for lqfp48 the following figure shows the engineering sample marking for the lqfp48 package. only the information field containing the engineering sample marking is shown. figure 35. lqfp48 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 8 q p d u n d e o h v x u i d f h 0 d u n l q j f r p s r v l w l r q i l h o g ( 6 ( q j l q h h u l q j v d p s o h p d u n l q j 0 6 9 package characteristics stm32f042xx 98/117 docid025832 rev 2 figure 36. ufqfpn48 ? 7 mm x 7 mm, 0.5 mm pitch, package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of the ufqfpn package. it is recommended to connect and solder this back-side pad to pcb ground. $ % b 0 ( b 9 ' 3 l q l g h q w l i l h u o d v h u p d u n l q j d u h d ( ( ' < ' ( ( [ s r v h g s d g d u h d = ' h w d l o = 5 w \ s / & [ ? s l q f r u q h u $ 6 h d w l q j s o d q h $ e h g g g ' h w d l o < 7 docid025832 rev 2 99/117 stm32f042xx package characteristics 115 figure 37. ufqfpn48 recommended footprint 1. dimensions are in millimeters. table 66. ufqfpn48 ? 7 mm x 7 mm, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 d 6.900 7.000 7.100 0.2717 0.2756 0.2795 e 6.900 7.000 7.100 0.2717 0.2756 0.2795 d2 5.500 5.600 5.700 0.2165 0.2205 0.2244 e2 5.500 5.600 5.700 0.2165 0.2205 0.2244 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 t - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - 7.30 7.30 0.20 0.30 0.55 0.50 5.80 6.20 6.20 5.60 5.60 5.80 0.75 ai15697 48 1 12 13 24 25 36 37 package characteristics stm32f042xx 100/117 docid025832 rev 2 marking of engineering samples for ufqfpn48 the following figure shows the engineering sample marking for the ufqfpn48 package. only the information field containing the engineering sample marking is shown. figure 38. ufqfpn48 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. ( q j l q h h u l q j v d p s o h 0 6 9 ( 6 docid025832 rev 2 101/117 stm32f042xx package characteristics 115 figure 39. wlcsp36 - 0.4 mm pitch, package outline 1. drawing is not to scale. $ r u l h q w d w l r q u h i h u h q f h : d i h u e d f n v l g h ' h w d l o $ u r w d w h g ? 6 h d w l q j s o d q h $ % x p s e 6 l g h y l h z $ $ ' h w d l o $ h ) * h h $ e d o o o r f d w l r q h % x p s v l g h h h h = $ = / b 0 ( b 9 * $ $ = ; < = f f f g g g ? e e d o o v = package characteristics stm32f042xx 102/117 docid025832 rev 2 table 67. wlcsp36, 0.4 mm pitch, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.555 0.525 0.585 0.0219 0.0207 0.0230 a1 0.175 - - 0.0069 - - a2 0.380 - - 0.0150 - - a3 (2) 2. back side coating 0.025 - - 0.0010 - - b (3) 3. dimension is measured at the maximum bump diameter parallel to primary datum z. 0.250 0.220 0.280 0.0098 0.0087 0.0110 d 2.605 2.570 2.640 0.1026 0.1012 0.1039 e 2.703 2.668 2.738 0.1064 0.1050 0.1078 e 0.400 - - 0.0157 - - e1 2.000 - - 0.0787 - - e2 2.000 - - 0.0787 - - f 0.3025 - - 0.0119 - - g 0.2825 - - 0.0111 - - ccc 0.100 - - 0.0039 - - ddd 0.050 - - 0.0020 - - eee 0.050 - - 0.0020 - - docid025832 rev 2 103/117 stm32f042xx package characteristics 115 marking of engineering samples for wlcsp36 the following figure shows the engineering sample marking for the wlcsp36 package. only the information field containing the engineering sample marking is shown. figure 40. wlcsp36 package top view 1. samples marked ?e? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. ( q j l q h h u l q j v d p s o h 0 6 9 ( package characteristics stm32f042xx 104/117 docid025832 rev 2 figure 41. lqfp32 ? 7 mm x 7 mm 32-pin low-profile quad flat package outline 1. drawing is not to scale. $ $ $ % % % ! , , + ! ! ! c b ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % # 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # 7 @ . & @ 7 e table 68. lqfp32 ? 7 mm x 7 mm 32-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 docid025832 rev 2 105/117 stm32f042xx package characteristics 115 figure 42. lqfp32 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.600 - - 0.2205 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.100 - - 0.0039 1. values in inches are converted from mm and rounded to 4 decimal digits. table 68. lqfp32 ? 7 mm x 7 mm 32-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max 6 ? & 0 ? 6 package characteristics stm32f042xx 106/117 docid025832 rev 2 marking of engineering samples for lqfp32 the following figure shows the engineering sample marking for the lqfp32 package. only the information field containing the engineering sample marking is shown. figure 43. lqfp32 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. ( 6 ( q j l q h h u l q j v d p s o h 0 6 9 docid025832 rev 2 107/117 stm32f042xx package characteristics 115 figure 44. ufqfpn32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of the ufqfpn package. this pad is used for the device ground and must be connected. it is referred to as pin 0 in table 12: legend/abbreviations used in the pinout table . se a ting pl a ne ddd c c a 3 a1 a d e 9 16 17 24 3 2 pin # 1 id r = 0. 3 0 8 e l l d2 1 b e2 a0b 8 _me bottom view table 69. ufqfpn32 ? 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package mechanical data dim. millimeters inches (1) min typ max min typ max a 0.5 0.55 0.6 0.0197 0.0217 0.0236 a1 0.00 0.02 0.05 0 0.0008 0.0020 a3 - 0.152 - - 0.006 - b 0.18 0.23 0.28 0.0071 0.0091 0.0110 d 4.90 5.00 5.10 0.1929 0.1969 0.2008 d2 - 3.50 - - 0.1378 - e 4.90 5.00 5.10 0.1929 0.1969 0.2008 e2 3.40 3.50 3.60 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - l 0.30 0.40 0.50 0.0118 0.0157 0.0197 ddd 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f042xx 108/117 docid025832 rev 2 figure 45. ufqfpn32 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. marking of engineering samples for ufqfpn32 the following figure shows the engineering sample marking for the ufqfpn32 package. only the information field containing the engineering sample marking is shown. figure 46. ufqfpn32 package top view 1. samples marked ?e? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. e engineering sample 1 ms34954v1 docid025832 rev 2 109/117 stm32f042xx package characteristics 115 figure 47. ufqfpn28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline 1. drawing is not to scale. 2. dimensions are in millimeters. 3. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. x 4 e b 3 e a t i n g 0 l a n e ! ! # o x ? 0 i n c o r n e r , , 2 o 4 y p $ e t a i l : $ $ % % 0 i n ) $ 3 e a t i n g 0 l a n e " ! $ e t a i l : ! " ? - % ? 6 table 70. ufqfpn28 ? 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.5 0.55 0.6 0.0197 0.0217 0.0236 a1 -0.05 0 0.05 -0.002 0 0.002 d 3.9 4 4.1 0.1535 0.1575 0.1614 d1 2.9 3 3.1 0.1142 0.1181 0.122 e 3.9 4 4.1 0.1535 0.1575 0.1614 e1 2.9 3 3.1 0.1142 0.1181 0.122 l 0.3 0.4 0.5 0.0118 0.0157 0.0197 l1 0.25 0.35 0.45 0.0098 0.0138 0.0177 t - 0.152 - - 0.006 - b 0.2 0.25 0.3 0.0079 0.0098 0.0118 e - 0.5 - - 0.0197 - 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f042xx 110/117 docid025832 rev 2 figure 48. ufqfpn28 recommended footprint 1. dimensions are in millimeters 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. ! " ? - % ? & 0 docid025832 rev 2 111/117 stm32f042xx package characteristics 115 marking of engineering samples for ufqfpn28 the following figure shows the engineering sample marking for the ufqfpn28 package. only the information field containing the engineering sample marking is shown. figure 49. ufqfpn28 package top view 1. samples marked ?e? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 0 6 9 ( ( q j l q h h u l q j v d p s o h package characteristics stm32f042xx 112/117 docid025832 rev 2 figure 50. tssop20 - 20-pin thin shrink small outline 1. drawing is not to scale. 9 ! ? - % # 0 c , % % $ ! ! k e b ! , a a a table 71. tssop20 ? 20-pin thin shrink small outline package mechanical data symbol millimeters inches (1) min typ max min typ a - 1.2 - - 0.0472 a1 0.05 - 0.15 0.002 - 0.0059 a2 0.8 1 1.05 0.0315 0.0394 0.0413 b 0.19 0.3 0.0075 - 0.0118 c 0.09 0.2 0.0035 - 0.0079 d (2) 6.4 6.5 6.6 0.252 0.2559 0.2598 e 6.2 6.4 6.6 0.2441 0.252 0.2598 e1 (3) 4.3 4.4 4.5 0.1693 0.1732 0.1772 e - 0.65 - - 0.0256 - l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 - 1 - - 0.0394 - k 0.0 - 8.0 0.0 - 8.0 aaa - - 0.1 - - 0.0039 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 3. dimension ?e1? does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.25mm per side. docid025832 rev 2 113/117 stm32f042xx package characteristics 115 figure 51. tssop20 recommended footprint 1. dimensions are in millimeters. marking of engineering samples for tssop20 the following figure shows the engineering sample marking for the tssop20 package. only the information field containing the engineering sample marking is shown. figure 52. tssop20 package top view 1. samples marked ?e? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. ( ( q j l q h h u l q j v d p s o h 0 6 9 package characteristics stm32f042xx 114/117 docid025832 rev 2 7.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 21: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ? ja ) where: ? t a max is the maximum ambient temperature in c, ?? ja is the package junction-to-ambient thermal resistance, in ? c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ?? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org table 72. package thermal characteristics symbol parameter value unit ? ja thermal resistance junction-ambient lqfp48 - 7 mm x 7 mm 55 c/w thermal resistance junction-ambient ufqfpn48 - 7 mm x 7 mm 33 thermal resistance junction-ambient wlcsp36 die 445 64 thermal resistance junction-ambient lqfp32 - 7 mm x 7 mm 57 thermal resistance junction-ambient ufqfpn32 - 5 mm x 5 mm 38 thermal resistance junction-ambient ufqfpn28 - 4 mm x 4 mm 118 thermal resistance junction-ambient tssop20 - 6.5 mm x 6.4 mm 76 docid025832 rev 2 115/117 stm32f042xx part numbering 115 8 part numbering for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest st sales office. + table 73. ordering information scheme example : stm32 f 042 c 6 t 6 x device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 042 = stm32f042xx pin count f = 20 pins g = 28 pins k = 32 pins t = 36 pins c = 48 pins code size 4 = 16 kbytes of flash memory 6 = 32 kbytes of flash memory package p = tssop t = lqfp u = ufqfpn y = wlcsp temperature range 6 = ?40 to 85 c 7 = ?40 to 105 c options xxx = programmed parts tr = tape and reel revision history stm32f042xx 116/117 docid025832 rev 2 9 revision history table 74. document revision history date revision changes 25-feb-2014 1 initial release. 04-apr-2014 2 updated: ? the document status to datasheet - production data, ? table 10: stm32f042x usart implementation : added one table footnote. ? figure 3: lqfp48 48-pin package pinout (top view) , ? figure 8: uqfpn28 28-pin package (top view) , ? table 13: stm32f042x pin definitions , ? table 19: current characteristics , ? table 26: typical and maximum current consumption from vdd supply at vdd = 3.6 v , ? table 27: typical and maximum current consumption from the vdda supply , ? table 28: typical and maximum consumption in stop and standby modes , ? table 29: typical and maximum current consumption from the vbat supply , ? table 30: typical current consumption, code executing from flash, running from hse 8 mhz crystal , ? table 43: flash memory characteristics , ? table 45: ems characteristics , ? table 46: emi characteristics , ? table 50: i/o static characteristics , ? table 49: i/o current injection susceptibility , ? figure 13: power supply scheme , ? figure 22: tc and tta i/o input characteristics , ? figure 23: five volt tolerant (ft and ftf) i/o input characteristics . added the sample engineering sections for all the packages in chapter 7: package characteristics : ? figure 35: lqfp48 package top view , ? figure 38: ufqfpn48 package top view , ? figure 40: wlcsp36 package top view , ? figure 43: lqfp32 package top view , ? figure 46: ufqfpn32 package top view , ? figure 49: ufqfpn28 package top view , ? figure 52: tssop20 package top view . docid025832 rev 2 117/117 stm32f042xx 117 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industr y domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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